Patents by Inventor Veerbhan Kheterpal

Veerbhan Kheterpal has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11392667
    Abstract: Systems and methods of configuring an array of processors of an integrated circuit includes identifying a fast Fourier transform (FFT) matrix multiply of input data, wherein the FFT matrix multiply of the input data includes a bit-reversed input array, configuring the array of processing cores based on the bit-reversed input array, wherein the configuring the array of processing cores includes storing the input bits of the bit-reversed input array within memory circuits of distinct processing cores of an array of processing cores of the integrated circuit based on an input bit mapping that identifies a pre-determined storage location within the array of processing cores of each input bit of the bit-reversed input array, and performing matrix multiply computations between weight stages of the FFT matrix multiply and the input bits of the bit-reversed input array stored within the memory circuits of the distinct processing cores.
    Type: Grant
    Filed: December 20, 2021
    Date of Patent: July 19, 2022
    Assignee: quadric.io, Inc.
    Inventors: Aman Sikka, Nigel Drego, Daniel Firu, Veerbhan Kheterpal
  • Publication number: 20220197971
    Abstract: Systems and methods of configuring an array of processors of an integrated circuit includes identifying a fast Fourier transform (FFT) matrix multiply of input data, wherein the FFT matrix multiply of the input data includes a bit-reversed input array, configuring the array of processing cores based on the bit-reversed input array, wherein the configuring the array of processing cores includes storing the input bits of the bit-reversed input array within memory circuits of distinct processing cores of an array of processing cores of the integrated circuit based on an input bit mapping that identifies a pre-determined storage location within the array of processing cores of each input bit of the bit-reversed input array, and performing matrix multiply computations between weight stages of the FFT matrix multiply and the input bits of the bit-reversed input array stored within the memory circuits of the distinct processing cores.
    Type: Application
    Filed: December 20, 2021
    Publication date: June 23, 2022
    Inventors: Aman Sikka, Nigel Drego, Daniel Firu, Veerbhan Kheterpal
  • Patent number: 11301481
    Abstract: An integrated circuit may be provided with cryptocurrency mining capabilities. The integrated circuit may include control circuitry and a number of processing cores that complete a Secure Hash Algorithm 256 (SHA-256) function in parallel. Logic circuitry may be shared between multiple processing cores. Each processing core may perform sequential rounds of cryptographic hashing operations based on a hash input and message word inputs. The control circuitry may control the processing cores to complete the SHA-256 function over different search spaces. The shared logic circuitry may perform a subset of the sequential rounds for multiple processing cores. If desired, the shared logic circuitry may generate message word inputs for some of the sequential rounds across multiple processing cores. By sharing logic circuitry across cores, chip area consumption and power efficiency may be improved relative to scenarios where the cores are formed using only dedicated logic.
    Type: Grant
    Filed: July 31, 2019
    Date of Patent: April 12, 2022
    Assignee: 21, Inc.
    Inventors: Veerbhan Kheterpal, Daniel Firu, Nigel Drego
  • Patent number: 11270298
    Abstract: Mining circuitry may be used to mine digital currency such as bitcoins by computing solutions to a cryptographic puzzle. Successful computation of a solution to the cryptographic puzzle may provide a reward of the digital currency. The mining circuitry may partition the mined reward between a first digital wallet and a second digital wallet. The first digital wallet may be user-provided, whereas the second digital wallet may be hardcoded into the dedicated mining circuitry. The mining circuitry may include control circuitry and multiple processing core circuits. The control circuitry may control the processing cores to solve the cryptographic puzzle via exhaustive search over possible inputs to the cryptographic puzzle.
    Type: Grant
    Filed: April 14, 2014
    Date of Patent: March 8, 2022
    Assignee: 21, Inc.
    Inventors: Matthew Pauker, Nigel Drego, Veerbhan Kheterpal, Daniel Firu
  • Publication number: 20210334450
    Abstract: Systems and methods of implementing tile-level predication of a computing tile of an integrated circuit includes identifying a plurality of distinct predicate state values for each of a plurality of distinct processing cores of the computing tile; calculating one or more summed predicate state values for an entirety of the plurality of distinct processing cores based on performing a summation operation of the plurality of distinct predicate state values; propagating the one or more summed predicate state values to an instructions generating circuit of the integrated circuit; and identifying, by the instructions generating circuit, a tile-level predication for the computing tile based on input of the one or more summed predicate state values.
    Type: Application
    Filed: July 1, 2021
    Publication date: October 28, 2021
    Inventors: Nigel Drego, Mrinalini Ravichandran, Aman Sikka, Daniel Firu, Veerbhan Kheterpal
  • Publication number: 20210326078
    Abstract: A circuit that includes a plurality of array cores, each array core of the plurality of array cores comprising: a plurality of distinct data processing circuits; and a data queue register file; a plurality of border cores, each border core of the plurality of border cores comprising: at least a register file, wherein: [i] at least a subset of the plurality of border cores encompasses a periphery of a first subset of the plurality of array cores; and [ii] a combination of the plurality of array cores and the plurality of border cores define an integrated circuit array.
    Type: Application
    Filed: July 1, 2021
    Publication date: October 21, 2021
    Inventors: Nigel Drego, Aman Sikka, Mrinalini Ravichandran, Ananth Durbha, Robert Daniel Firu, Veerbhan Kheterpal
  • Publication number: 20210247981
    Abstract: In one embodiment, a method for improving a performance of an integrated circuit includes implementing one or more computing devices executing a compiler program that: (i) evaluates a target instruction set intended for execution by an integrated circuit; (ii) identifies one or more nested loop instructions within the target instruction set based on the evaluation; (iii) evaluates whether a most inner loop body within the one or more nested loop instructions comprises a candidate inner loop body that requires a loop optimization that mitigates an operational penalty to the integrated circuit based on one or more executional properties of the most inner loop instruction; and (iv) implements the loop optimization that modifies the target instruction set to include loop optimization instructions to control, at runtime, an execution and a termination of the most inner loop body thereby mitigating the operational penalty to the integrated circuit.
    Type: Application
    Filed: April 28, 2021
    Publication date: August 12, 2021
    Inventors: Nigel Drego, Mrinalini Ravichandran, Jianming Chang, Daniel Firu, Veerbhan Kheterpal
  • Patent number: 11087067
    Abstract: Systems and methods of implementing tile-level predication of a computing tile of an integrated circuit includes identifying a plurality of distinct predicate state values for each of a plurality of distinct processing cores of the computing tile; calculating one or more summed predicate state values for an entirety of the plurality of distinct processing cores based on performing a summation operation of the plurality of distinct predicate state values; propagating the one or more summed predicate state values to an instructions generating circuit of the integrated circuit; and identifying, by the instructions generating circuit, a tile-level predication for the computing tile based on input of the one or more summed predicate state values.
    Type: Grant
    Filed: January 6, 2021
    Date of Patent: August 10, 2021
    Assignee: quadric.io, Inc.
    Inventors: Nigel Drego, Mrinalini Ravichandran, Aman Sikka, Daniel Firu, Veerbhan Kheterpal
  • Patent number: 11086574
    Abstract: A circuit that includes a plurality of array cores, each array core of the plurality of array cores comprising: a plurality of distinct data processing circuits; and a data queue register file; a plurality of border cores, each border core of the plurality of border cores comprising: at least a register file, wherein: [i] at least a subset of the plurality of border cores encompasses a periphery of a first subset of the plurality of array cores; and [ii] a combination of the plurality of array cores and the plurality of border cores define an integrated circuit array.
    Type: Grant
    Filed: March 26, 2020
    Date of Patent: August 10, 2021
    Assignee: quadric.io, Inc.
    Inventors: Nigel Drego, Aman Sikka, Mrinalini Ravichandran, Ananth Durbha, Robert Daniel Firu, Veerbhan Kheterpal
  • Publication number: 20210224222
    Abstract: Systems and methods of propagating data within an integrated circuit includes: identifying a coarse data propagation path for distinct subsets of data of an input dataset that includes: setting inter-core data movements for the distinct subsets of data, the inter-core data movements defining a predetermined propagation of a given subset of data between two or more of a plurality of cores of an integrated circuit array of the integrated circuit; identifying a granular data propagation path for each distinct subset of data that includes: setting intra-core data movements for each distinct subset of data, the intra-core data movements defining a predetermined propagation of the given subset of data within one or more of the plurality of cores of the integrated circuit array of the integrated circuit; enabling a flow of the input dataset within the integrated circuit based on the coarse data propagation path and the granular propagation path.
    Type: Application
    Filed: April 5, 2021
    Publication date: July 22, 2021
    Inventors: Nigel Drego, Aman Sikka, Ananth Durbha, Mrinalini Ravichandran, Robert Daniel Firu, Veerbhan Kheterpal
  • Publication number: 20210216696
    Abstract: Systems and methods for virtually partitioning an integrated circuit includes identifying dimensional attributes of a target input dataset; selecting a data partitioning scheme from a plurality of distinct data partitioning schemes for the target input dataset based on: the dimensional attributes of the target dataset, and architectural attributes of an integrated circuit; disintegrating the target dataset into a plurality of distinct subsets of data based on the selected data partitioning scheme; identifying a virtual processing core partitioning scheme from a plurality of distinct processing core partitioning schemes for an architecture of the integrated circuit based on the disintegration of the target input dataset; virtually partitioning the architecture of the integrated circuit into a plurality of distinct partitions of processing cores of the integrated circuit; and mapping each of the plurality of distinct subsets of data to one of the plurality of distinct partitions of processing cores of the integ
    Type: Application
    Filed: March 26, 2021
    Publication date: July 15, 2021
    Inventors: Nigel Drego, Aman Sikka, Mrinalini Ravichandran, Robert Daniel Firu, Veerbhan Kheterpal
  • Patent number: 11061678
    Abstract: In one embodiment, a method for improving a performance of an integrated circuit includes implementing one or more computing devices executing a compiler program that: (i) evaluates a target instruction set intended for execution by an integrated circuit; (ii) identifies one or more nested loop instructions within the target instruction set based on the evaluation; (iii) evaluates whether a most inner loop body within the one or more nested loop instructions comprises a candidate inner loop body that requires a loop optimization that mitigates an operational penalty to the integrated circuit based on one or more executional properties of the most inner loop instruction; and (iv) implements the loop optimization that modifies the target instruction set to include loop optimization instructions to control, at runtime, an execution and a termination of the most inner loop body thereby mitigating the operational penalty to the integrated circuit.
    Type: Grant
    Filed: December 18, 2020
    Date of Patent: July 13, 2021
    Assignee: qaudric.io Inc
    Inventors: Nigel Drego, Mrinalini Ravichandran, Jianman Chang, Daniel Firu, Veerbhan Kheterpal
  • Publication number: 20210208889
    Abstract: In one embodiment, a method for improving a performance of an integrated circuit includes implementing one or more computing devices executing a compiler program that: (i) evaluates a target instruction set intended for execution by an integrated circuit; (ii) identifies one or more nested loop instructions within the target instruction set based on the evaluation; (iii) evaluates whether a most inner loop body within the one or more nested loop instructions comprises a candidate inner loop body that requires a loop optimization that mitigates an operational penalty to the integrated circuit based on one or more executional properties of the most inner loop instruction; and (iv) implements the loop optimization that modifies the target instruction set to include loop optimization instructions to control, at runtime, an execution and a termination of the most inner loop body thereby mitigating the operational penalty to the integrated circuit.
    Type: Application
    Filed: December 18, 2020
    Publication date: July 8, 2021
    Inventors: Nigel Drego, Mrinalini Ravichandran, Jianman Chang, Daniel Firu, Veerbhan Kheterpal
  • Publication number: 20210209286
    Abstract: Systems and methods of implementing tile-level predication of a computing tile of an integrated circuit includes identifying a plurality of distinct predicate state values for each of a plurality of distinct processing cores of the computing tile; calculating one or more summed predicate state values for an entirety of the plurality of distinct processing cores based on performing a summation operation of the plurality of distinct predicate state values; propagating the one or more summed predicate state values to an instructions generating circuit of the integrated circuit; and identifying, by the instructions generating circuit, a tile-level predication for the computing tile based on input of the one or more summed predicate state values.
    Type: Application
    Filed: January 6, 2021
    Publication date: July 8, 2021
    Inventors: Nigel Drego, Mrinalini Ravichandran, Aman Sikka, Daniel Firu, Veerbhan Kheterpal
  • Patent number: 10997115
    Abstract: Systems and methods of propagating data within an integrated circuit includes: identifying a coarse data propagation path for distinct subsets of data of an input dataset that includes: setting inter-core data movements for the distinct subsets of data, the inter-core data movements defining a predetermined propagation of a given subset of data between two or more of a plurality of cores of an integrated circuit array of the integrated circuit; identifying a granular data propagation path for each distinct subset of data that includes: setting intra-core data movements for each distinct subset of data, the intra-core data movements defining a predetermined propagation of the given subset of data within one or more of the plurality of cores of the integrated circuit array of the integrated circuit; enabling a flow of the input dataset within the integrated circuit based on the coarse data propagation path and the granular propagation path.
    Type: Grant
    Filed: March 5, 2019
    Date of Patent: May 4, 2021
    Assignee: quadric.io, Inc.
    Inventors: Nigel Drego, Aman Sikka, Ananth Durbha, Mrinalini Ravichandran, Robert Daniel Firu, Veerbhan Kheterpal
  • Patent number: 10990410
    Abstract: Systems and methods for virtually partitioning an integrated circuit may include identifying dimensional attributes of a target input dataset and selecting a data partitioning scheme from a plurality of distinct data partitioning schemes for the target input dataset based on the dimensional attributes of the target dataset and architectural attributes of an integrated circuit. The method may include disintegrating the target dataset into a plurality of distinct subsets of data based on the selected data partitioning scheme and identifying a virtual processing core partitioning scheme from a plurality of distinct processing core partitioning schemes for an architecture of the integrated circuit based on the disintegration of the target input dataset.
    Type: Grant
    Filed: May 1, 2020
    Date of Patent: April 27, 2021
    Assignee: quadric.io, Inc.
    Inventors: Nigel Drego, Aman Sikka, Mrinalini Ravichandran, Robert Daniel Firu, Veerbhan Kheterpal
  • Publication number: 20210019079
    Abstract: A system and method for random access augmented flow-based processing within an integrated circuit includes computing, by a plurality of distinct processing cores, a plurality of linear indices and associated valid bits; propagating the plurality of linear indices in a predetermined manner to a plurality of columns of first-in, first-out buffers; loading, from the FIFO buffers, the plurality of linear indices to a content addressable memory; at the CAM: coalescing redundant linear indices in each of the plurality of FIFO buffers; performing lookups for a plurality of memory addresses based on the plurality of linear indices; collecting at a read data buffer a plurality of distinct pieces of data from one of an on-chip memory based on the plurality of memory addresses; reading the plurality of distinct pieces of data from the read data buffer; and propagating the plurality of distinct pieces of data into the processing cores.
    Type: Application
    Filed: September 25, 2020
    Publication date: January 21, 2021
    Inventors: Nigel Drego, Aman Sikka, Mrinalini Ravichandran, Robert Daniel Firu, Veerbhan Kheterpal
  • Publication number: 20200412544
    Abstract: Devices and circuitry for computing hash values.
    Type: Application
    Filed: September 10, 2020
    Publication date: December 31, 2020
    Inventors: Veerbhan Kheterpal, Daniel Firu, Nigel Drego
  • Publication number: 20200410488
    Abstract: Systems and methods for accessing remote digital services by using embedded circuitry included in an electronic device.
    Type: Application
    Filed: September 10, 2020
    Publication date: December 31, 2020
    Inventors: Balaji S. Srinivasan, Daniel Firu, Veerbhan Kheterpal, Nigel Drego
  • Patent number: 10839378
    Abstract: A first device may be coupled to a second device over a network. The first device may maintain a first cryptocurrency wallet and may include mining circuitry that generates cryptocurrency rewards for the wallet. The first device may transmit a communications request to the second device. The second device may transmit payment information identifying a second wallet and a selected authentication amount to the first device. The second device may select the authentication amount to perform a desired amount of device connection rate limiting. The first device may generate an authentication transaction for a cryptocurrency network to transfer the authentication amount from the first wallet to the second wallet. The second device may determine whether the authentication transaction has been verified by the cryptocurrency network. In response to determining that the authentication transaction has been verified by the cryptocurrency network, the second device may establish the communication link.
    Type: Grant
    Filed: January 12, 2016
    Date of Patent: November 17, 2020
    Assignee: 21, Inc.
    Inventors: Balaji S. Srinivasan, Daniel Firu, Veerbhan Kheterpal, Nigel Drego