Patents by Inventor Veerendra Bhora
Veerendra Bhora has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20160323881Abstract: Methods, systems, and devices are described for wireless communication. An example wireless communication device may receive at least a portion of a data frame from another wireless communication device via a first or primary channel. The example wireless communication device may transmit a first acknowledgement message via a second or alternate channel, different from the first or primary channel, in response to the received data frame. In another example, an example wireless communication device may transmit a data frame via a first or primary channel. The wireless communication device may receive an acknowledgement message via a second or alternate channel, different from the first or primary channel in response to the data frame from another wireless communication device.Type: ApplicationFiled: April 28, 2016Publication date: November 3, 2016Inventors: Veerendra Bhora, Simone Merlin, Vincent Knowles Jones, IV, Hemanth Sampath, Assaf Touboul, Adam Lapede
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Patent number: 9363755Abstract: Various aspects of apparatus for accessing a network through a wireless access point and methods of power savings for such apparatus include autonomously alternating between a listen state and the sleep state during a time period in which no data is detected from the remote apparatus, and progressively increase the sleep state interval during the time period for at least a portion of the time period.Type: GrantFiled: May 21, 2013Date of Patent: June 7, 2016Assignee: QUALCOMM IncorporatedInventors: Sarvesh Shrivastava, Sandip Homchaudhuri, Shu Du, Zhanfeng Jia, Veerendra Bhora
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Patent number: 9167530Abstract: Various aspects of apparatus for accessing a network through a wireless access point and methods of power savings for such apparatus include scheduling a sleep state interval, entering a sleep state at the beginning of the scheduled sleep interval, and buffering data during the sleep state for transmission following the sleep state.Type: GrantFiled: May 21, 2013Date of Patent: October 20, 2015Assignee: QUALCOMM IncorporatedInventors: Sarvesh Shrivastava, Sandip Homchaudhuri, Shu Du, Zhanfeng Jia, Veerendra Bhora
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Patent number: 9119157Abstract: Various aspects of apparatus for accessing a network through a wireless access point and methods of power savings for such apparatus include operating in a sleep state, and scheduling one or more sleep state intervals for operating in the sleep state during a time period, wherein the scheduled one or more sleep state intervals are based on one or more wireless transmission parameters.Type: GrantFiled: May 21, 2013Date of Patent: August 25, 2015Assignee: QUALCOMM IncorporatedInventors: Sarvesh Shrivastava, Sandip Homchaudhuri, Shu Du, Zhanfeng Jia, Veerendra Bhora
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Publication number: 20140153459Abstract: Various aspects of apparatus for accessing a network through a wireless access point and methods of power savings for such apparatus include autonomously alternating between a listen state and the sleep state during a time period in which no data is detected from the remote apparatus, and progressively increase the sleep state interval during the time period for at least a portion of the time period.Type: ApplicationFiled: May 21, 2013Publication date: June 5, 2014Applicant: QUALCOMM IncorporatedInventors: Sarvesh SHRIVASTAVA, Sandip HOMCHAUDHURI, Shu DU, Zhanfeng JIA, Veerendra BHORA
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Publication number: 20140153458Abstract: Various aspects of apparatus for accessing a network through a wireless access point and methods of power savings for such apparatus include scheduling a sleep state interval, entering a sleep state at the beginning of the scheduled sleep interval, and buffering data during the sleep state for transmission following the sleep state.Type: ApplicationFiled: May 21, 2013Publication date: June 5, 2014Applicant: QUALCOMM IncorporatedInventors: Sarvesh SHRIVASTAVA, Sandip HOMCHAUDHURI, Shu DU, Zhanfeng JIA, Veerendra BHORA
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Publication number: 20140153460Abstract: Various aspects of apparatus for accessing a network through a wireless access point and methods of power savings for such apparatus include operating in a sleep state, and scheduling one or more sleep state intervals for operating in the sleep state during a time period, wherein the scheduled one or more sleep state intervals are based on one or more wireless transmission parameters.Type: ApplicationFiled: May 21, 2013Publication date: June 5, 2014Inventors: Sarvesh SHRIVASTAVA, Sandip HOMCHAUDHURI, Shu DU, Zhanfeng JIA, Veerendra BHORA
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Patent number: 8068566Abstract: In general, in one aspect, the disclosure describes a unified simplified maximum likelihood detector to be utilized with multiple input multiple output (MIMO) receivers to estimate transmitted signals. The unified detector includes a common framework capable of being utilized for multiple detection modes and multiple MIMO configurations.Type: GrantFiled: July 31, 2007Date of Patent: November 29, 2011Assignee: Intel CorporationInventors: Raghavan Sudhakar, Veerendra Bhora, Kamal J. Koshy
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Patent number: 7992075Abstract: A method for encoding data is disclosed. The method can include receiving a first bit segment (K?1 bits) from a bit stream, storing the first bit segment, initializing an encoder with the first bit segment, start encoding and transmitting from the Kth bit to the end of the appended data stream, and appending the first bit segment (K?1 bits) to the end of the data stream. The disclose arrangements can be similar to tail-biting methods different in that the initial bits are utilized to initialize the encoded as opposed to the tail or last bit as provided by tailbiting methods.Type: GrantFiled: March 19, 2007Date of Patent: August 2, 2011Assignee: Intel CorporationInventor: Veerendra Bhora
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Patent number: 7895506Abstract: Embodiments of an iterative decoder with early-exit condition detection and methods for decoding are generally described herein. Other embodiments may be described and claimed. In some embodiments, a first codeword is generated from decoded bits after one or more half-iterations of an iterative decoder, a second codeword from decoded bits after an additional half-iteration of the iterative decoder, and the first and second codewords are compared to determine whether the decoded bits are valid. In some embodiments, double or triple codeword matching is selected based on an estimated signal-to-noise ratio (SNR) and the modulation level.Type: GrantFiled: December 18, 2006Date of Patent: February 22, 2011Assignee: Intel CorporationInventors: Veerendra Bhora, Raghavan Sudhakar
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Publication number: 20090034662Abstract: In general, in one aspect, the disclosure describes a unified simplified maximum likelihood detector to be utilized with multiple input multiple output (MIMO) receivers to estimate transmitted signals. The unified detector includes a common framework capable of being utilized for multiple spatial operational modes and multiple MIMO configurations.Type: ApplicationFiled: July 31, 2007Publication date: February 5, 2009Inventors: Raghavan Sudhakar, Veerendra Bhora, Kamal J. Koshy
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Publication number: 20080231479Abstract: A method for encoding data is disclosed. The method can include receiving a first bit segment (K?1 bits) from a bit stream, storing the first bit segment, initializing an encoder with the first bit segment, start encoding and transmitting from the Kth bit to the end of the appended data stream, and appending the first bit segment (K?1 bits) to the end of the data stream. The disclose arrangements can be similar to tail-biting methods different in that the initial bits are utilized to initialize the encoded as opposed to the tail or last bit as provided by tailbiting methods.Type: ApplicationFiled: March 19, 2007Publication date: September 25, 2008Inventor: Veerendra Bhora
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Publication number: 20080148125Abstract: Embodiments of an iterative decoder with early-exit condition detection and methods for decoding are generally described herein. Other embodiments may be described and claimed. In some embodiments, a first codeword is generated from decoded bits after one or more half-iterations of an iterative decoder, a second codeword from decoded bits after an additional half-iteration of the iterative decoder, and the first and second codewords are compared to determine whether the decoded bits are valid. In some embodiments, double or triple codeword matching is selected based on an estimated signal-to-noise ratio (SNR) and the modulation level.Type: ApplicationFiled: December 18, 2006Publication date: June 19, 2008Inventors: Veerendra Bhora, Raghavan Sudhakar
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Patent number: 7036067Abstract: According to an embodiment of the invention, a method and apparatus are described for error detection for multi-stream communication. Under an embodiment of the invention, a method for producing an error word for a data stream comprises computing an intermediate error word for each of a plurality of data sub-streams, the data stream being equivalent to a concatenation of the plurality of data sub-streams; and combining the intermediate error words to produce the error word for the data stream.Type: GrantFiled: March 28, 2003Date of Patent: April 25, 2006Assignee: ArrayComm, LLCInventors: Pulakesh Roy, Tibor Boros, Veerendra Bhora
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Patent number: 6996163Abstract: In one embodiment, a Walsh-Hadamard decoder can have a hardware efficient Fast Hadamard Transform (“FHT”) engine. In one embodiment, the FHT engine can include an input to receive an input sequence to be decoded into a Walsh-Hadamard codeword. The FHT engine can further include a controller to correlate the received input sequence with a plurality of Walsh-Hadamard codewords using two add/subtract modules. In one embodiment, the two add/subtract modules operate in parallel.Type: GrantFiled: March 27, 2003Date of Patent: February 7, 2006Assignee: ArrayComm, Inc.Inventors: Veerendra Bhora, Pulakesh Roy, Tibor Boros
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Publication number: 20040190604Abstract: In one embodiment, a Walsh-Hadamard decoder can have a hardware efficient Fast Hadamard Transform (“FHT”) engine. In one embodiment, the FHT engine can include an input to receive an input sequence to be decoded into a Walsh-Hadamard codeword. The FHT engine can further include a controller to correlate the received input sequence with a plurality of Walsh-Hadamard codewords using two add/subtract modules. In one embodiment, the two add/subtract modules operate in parallel.Type: ApplicationFiled: March 27, 2003Publication date: September 30, 2004Inventors: Veerendra Bhora, Pulakesh Roy, Tibor Boros
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Publication number: 20040193993Abstract: According to an embodiment of the invention, a method and apparatus are described for error detection for multi-stream communication. Under an embodiment of the invention, a method for producing an error word for a data stream comprises computing an intermediate error word for each of a plurality of data sub-streams, the data stream being equivalent to a concatenation of the plurality of data sub-streams; and combining the intermediate error words to produce the error word for the data stream.Type: ApplicationFiled: March 28, 2003Publication date: September 30, 2004Inventors: Pulakesh Roy, Tibor Boros, Veerendra Bhora
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Publication number: 20040193982Abstract: The present invention allows a complex digital processing engine to be tested automatically and autonomously using a minimum of memory and processing resources. In one embodiment, the invention includes an input buffer to store a digital test sequence, a digital data modulator coupled to the input buffer to generate a modulated digital sample sequence using the test sequence, a test buffer coupled to the modulator to receive and store a representation of the sample sequence, and a test buffer output to enable the test buffer contents to be compared to a reference sequence.Type: ApplicationFiled: March 31, 2003Publication date: September 30, 2004Applicant: ArrayComm, Inc.Inventors: Veerendra Bhora, Tibor Boros, Pulakesh Roy
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Publication number: 20040193985Abstract: The present invention allows a complex digital processing engine to be tested automatically and autonomously using a minimum of memory and processing resources. In one embodiment, the invention includes a test controller integrated on an IC, a test pattern generator coupled to the controller to provide a test pattern upon receiving a controller command, and a unit under test integrated on the IC coupled to the test controller to receive a start signal from the test controller to apply an operation to the test pattern, the operation generating a test output. It further includes a test buffer integrated on the IC coupled to the unit under test to receive and store a representation of the test output, a reference memory integrated on the IC to store a reference value, and a comparator integrated on the IC coupled to the test controller to compare the test buffer contents to the stored reference value and to provide a test result signal to the test.Type: ApplicationFiled: March 31, 2003Publication date: September 30, 2004Inventors: Veerendra Bhora, Tibor Boros, Pulakesh Roy