Patents by Inventor Veerendra Bhora

Veerendra Bhora has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20160323881
    Abstract: Methods, systems, and devices are described for wireless communication. An example wireless communication device may receive at least a portion of a data frame from another wireless communication device via a first or primary channel. The example wireless communication device may transmit a first acknowledgement message via a second or alternate channel, different from the first or primary channel, in response to the received data frame. In another example, an example wireless communication device may transmit a data frame via a first or primary channel. The wireless communication device may receive an acknowledgement message via a second or alternate channel, different from the first or primary channel in response to the data frame from another wireless communication device.
    Type: Application
    Filed: April 28, 2016
    Publication date: November 3, 2016
    Inventors: Veerendra Bhora, Simone Merlin, Vincent Knowles Jones, IV, Hemanth Sampath, Assaf Touboul, Adam Lapede
  • Patent number: 9363755
    Abstract: Various aspects of apparatus for accessing a network through a wireless access point and methods of power savings for such apparatus include autonomously alternating between a listen state and the sleep state during a time period in which no data is detected from the remote apparatus, and progressively increase the sleep state interval during the time period for at least a portion of the time period.
    Type: Grant
    Filed: May 21, 2013
    Date of Patent: June 7, 2016
    Assignee: QUALCOMM Incorporated
    Inventors: Sarvesh Shrivastava, Sandip Homchaudhuri, Shu Du, Zhanfeng Jia, Veerendra Bhora
  • Patent number: 9167530
    Abstract: Various aspects of apparatus for accessing a network through a wireless access point and methods of power savings for such apparatus include scheduling a sleep state interval, entering a sleep state at the beginning of the scheduled sleep interval, and buffering data during the sleep state for transmission following the sleep state.
    Type: Grant
    Filed: May 21, 2013
    Date of Patent: October 20, 2015
    Assignee: QUALCOMM Incorporated
    Inventors: Sarvesh Shrivastava, Sandip Homchaudhuri, Shu Du, Zhanfeng Jia, Veerendra Bhora
  • Patent number: 9119157
    Abstract: Various aspects of apparatus for accessing a network through a wireless access point and methods of power savings for such apparatus include operating in a sleep state, and scheduling one or more sleep state intervals for operating in the sleep state during a time period, wherein the scheduled one or more sleep state intervals are based on one or more wireless transmission parameters.
    Type: Grant
    Filed: May 21, 2013
    Date of Patent: August 25, 2015
    Assignee: QUALCOMM Incorporated
    Inventors: Sarvesh Shrivastava, Sandip Homchaudhuri, Shu Du, Zhanfeng Jia, Veerendra Bhora
  • Publication number: 20140153459
    Abstract: Various aspects of apparatus for accessing a network through a wireless access point and methods of power savings for such apparatus include autonomously alternating between a listen state and the sleep state during a time period in which no data is detected from the remote apparatus, and progressively increase the sleep state interval during the time period for at least a portion of the time period.
    Type: Application
    Filed: May 21, 2013
    Publication date: June 5, 2014
    Applicant: QUALCOMM Incorporated
    Inventors: Sarvesh SHRIVASTAVA, Sandip HOMCHAUDHURI, Shu DU, Zhanfeng JIA, Veerendra BHORA
  • Publication number: 20140153458
    Abstract: Various aspects of apparatus for accessing a network through a wireless access point and methods of power savings for such apparatus include scheduling a sleep state interval, entering a sleep state at the beginning of the scheduled sleep interval, and buffering data during the sleep state for transmission following the sleep state.
    Type: Application
    Filed: May 21, 2013
    Publication date: June 5, 2014
    Applicant: QUALCOMM Incorporated
    Inventors: Sarvesh SHRIVASTAVA, Sandip HOMCHAUDHURI, Shu DU, Zhanfeng JIA, Veerendra BHORA
  • Publication number: 20140153460
    Abstract: Various aspects of apparatus for accessing a network through a wireless access point and methods of power savings for such apparatus include operating in a sleep state, and scheduling one or more sleep state intervals for operating in the sleep state during a time period, wherein the scheduled one or more sleep state intervals are based on one or more wireless transmission parameters.
    Type: Application
    Filed: May 21, 2013
    Publication date: June 5, 2014
    Inventors: Sarvesh SHRIVASTAVA, Sandip HOMCHAUDHURI, Shu DU, Zhanfeng JIA, Veerendra BHORA
  • Patent number: 8068566
    Abstract: In general, in one aspect, the disclosure describes a unified simplified maximum likelihood detector to be utilized with multiple input multiple output (MIMO) receivers to estimate transmitted signals. The unified detector includes a common framework capable of being utilized for multiple detection modes and multiple MIMO configurations.
    Type: Grant
    Filed: July 31, 2007
    Date of Patent: November 29, 2011
    Assignee: Intel Corporation
    Inventors: Raghavan Sudhakar, Veerendra Bhora, Kamal J. Koshy
  • Patent number: 7992075
    Abstract: A method for encoding data is disclosed. The method can include receiving a first bit segment (K?1 bits) from a bit stream, storing the first bit segment, initializing an encoder with the first bit segment, start encoding and transmitting from the Kth bit to the end of the appended data stream, and appending the first bit segment (K?1 bits) to the end of the data stream. The disclose arrangements can be similar to tail-biting methods different in that the initial bits are utilized to initialize the encoded as opposed to the tail or last bit as provided by tailbiting methods.
    Type: Grant
    Filed: March 19, 2007
    Date of Patent: August 2, 2011
    Assignee: Intel Corporation
    Inventor: Veerendra Bhora
  • Patent number: 7895506
    Abstract: Embodiments of an iterative decoder with early-exit condition detection and methods for decoding are generally described herein. Other embodiments may be described and claimed. In some embodiments, a first codeword is generated from decoded bits after one or more half-iterations of an iterative decoder, a second codeword from decoded bits after an additional half-iteration of the iterative decoder, and the first and second codewords are compared to determine whether the decoded bits are valid. In some embodiments, double or triple codeword matching is selected based on an estimated signal-to-noise ratio (SNR) and the modulation level.
    Type: Grant
    Filed: December 18, 2006
    Date of Patent: February 22, 2011
    Assignee: Intel Corporation
    Inventors: Veerendra Bhora, Raghavan Sudhakar
  • Publication number: 20090034662
    Abstract: In general, in one aspect, the disclosure describes a unified simplified maximum likelihood detector to be utilized with multiple input multiple output (MIMO) receivers to estimate transmitted signals. The unified detector includes a common framework capable of being utilized for multiple spatial operational modes and multiple MIMO configurations.
    Type: Application
    Filed: July 31, 2007
    Publication date: February 5, 2009
    Inventors: Raghavan Sudhakar, Veerendra Bhora, Kamal J. Koshy
  • Publication number: 20080231479
    Abstract: A method for encoding data is disclosed. The method can include receiving a first bit segment (K?1 bits) from a bit stream, storing the first bit segment, initializing an encoder with the first bit segment, start encoding and transmitting from the Kth bit to the end of the appended data stream, and appending the first bit segment (K?1 bits) to the end of the data stream. The disclose arrangements can be similar to tail-biting methods different in that the initial bits are utilized to initialize the encoded as opposed to the tail or last bit as provided by tailbiting methods.
    Type: Application
    Filed: March 19, 2007
    Publication date: September 25, 2008
    Inventor: Veerendra Bhora
  • Publication number: 20080148125
    Abstract: Embodiments of an iterative decoder with early-exit condition detection and methods for decoding are generally described herein. Other embodiments may be described and claimed. In some embodiments, a first codeword is generated from decoded bits after one or more half-iterations of an iterative decoder, a second codeword from decoded bits after an additional half-iteration of the iterative decoder, and the first and second codewords are compared to determine whether the decoded bits are valid. In some embodiments, double or triple codeword matching is selected based on an estimated signal-to-noise ratio (SNR) and the modulation level.
    Type: Application
    Filed: December 18, 2006
    Publication date: June 19, 2008
    Inventors: Veerendra Bhora, Raghavan Sudhakar
  • Patent number: 7036067
    Abstract: According to an embodiment of the invention, a method and apparatus are described for error detection for multi-stream communication. Under an embodiment of the invention, a method for producing an error word for a data stream comprises computing an intermediate error word for each of a plurality of data sub-streams, the data stream being equivalent to a concatenation of the plurality of data sub-streams; and combining the intermediate error words to produce the error word for the data stream.
    Type: Grant
    Filed: March 28, 2003
    Date of Patent: April 25, 2006
    Assignee: ArrayComm, LLC
    Inventors: Pulakesh Roy, Tibor Boros, Veerendra Bhora
  • Patent number: 6996163
    Abstract: In one embodiment, a Walsh-Hadamard decoder can have a hardware efficient Fast Hadamard Transform (“FHT”) engine. In one embodiment, the FHT engine can include an input to receive an input sequence to be decoded into a Walsh-Hadamard codeword. The FHT engine can further include a controller to correlate the received input sequence with a plurality of Walsh-Hadamard codewords using two add/subtract modules. In one embodiment, the two add/subtract modules operate in parallel.
    Type: Grant
    Filed: March 27, 2003
    Date of Patent: February 7, 2006
    Assignee: ArrayComm, Inc.
    Inventors: Veerendra Bhora, Pulakesh Roy, Tibor Boros
  • Publication number: 20040190604
    Abstract: In one embodiment, a Walsh-Hadamard decoder can have a hardware efficient Fast Hadamard Transform (“FHT”) engine. In one embodiment, the FHT engine can include an input to receive an input sequence to be decoded into a Walsh-Hadamard codeword. The FHT engine can further include a controller to correlate the received input sequence with a plurality of Walsh-Hadamard codewords using two add/subtract modules. In one embodiment, the two add/subtract modules operate in parallel.
    Type: Application
    Filed: March 27, 2003
    Publication date: September 30, 2004
    Inventors: Veerendra Bhora, Pulakesh Roy, Tibor Boros
  • Publication number: 20040193993
    Abstract: According to an embodiment of the invention, a method and apparatus are described for error detection for multi-stream communication. Under an embodiment of the invention, a method for producing an error word for a data stream comprises computing an intermediate error word for each of a plurality of data sub-streams, the data stream being equivalent to a concatenation of the plurality of data sub-streams; and combining the intermediate error words to produce the error word for the data stream.
    Type: Application
    Filed: March 28, 2003
    Publication date: September 30, 2004
    Inventors: Pulakesh Roy, Tibor Boros, Veerendra Bhora
  • Publication number: 20040193982
    Abstract: The present invention allows a complex digital processing engine to be tested automatically and autonomously using a minimum of memory and processing resources. In one embodiment, the invention includes an input buffer to store a digital test sequence, a digital data modulator coupled to the input buffer to generate a modulated digital sample sequence using the test sequence, a test buffer coupled to the modulator to receive and store a representation of the sample sequence, and a test buffer output to enable the test buffer contents to be compared to a reference sequence.
    Type: Application
    Filed: March 31, 2003
    Publication date: September 30, 2004
    Applicant: ArrayComm, Inc.
    Inventors: Veerendra Bhora, Tibor Boros, Pulakesh Roy
  • Publication number: 20040193985
    Abstract: The present invention allows a complex digital processing engine to be tested automatically and autonomously using a minimum of memory and processing resources. In one embodiment, the invention includes a test controller integrated on an IC, a test pattern generator coupled to the controller to provide a test pattern upon receiving a controller command, and a unit under test integrated on the IC coupled to the test controller to receive a start signal from the test controller to apply an operation to the test pattern, the operation generating a test output. It further includes a test buffer integrated on the IC coupled to the unit under test to receive and store a representation of the test output, a reference memory integrated on the IC to store a reference value, and a comparator integrated on the IC coupled to the test controller to compare the test buffer contents to the stored reference value and to provide a test result signal to the test.
    Type: Application
    Filed: March 31, 2003
    Publication date: September 30, 2004
    Inventors: Veerendra Bhora, Tibor Boros, Pulakesh Roy