Patents by Inventor Veeresh GARAG

Veeresh GARAG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Encoded on-die termination for efficient multipackage termination
    Patent number: 11750190
    Abstract: On-die termination (ODT) is triggered through a serial signal encoding on an ODT signal line instead of a simple binary enable signal. An ODT circuit applies one of multiple termination impedances based on the ODT signal encoding. An ODT enable signal line receives an ODT enable signal as multiple serial bits to encode the selected termination impedance, to cause the ODT circuit to apply the selected termination impedance.
    Type: Grant
    Filed: December 14, 2020
    Date of Patent: September 5, 2023
    Assignee: Intel Corporation
    Inventors: Sheldon G. Hiemstra, Veeresh Garag
  • TECHNOLOGIES FOR ON-MEMORY DIE VOLTAGE REGULATOR
    Publication number: 20230093729
    Abstract: Techniques for an on-memory die voltage regulator is disclosed. In the illustrative embodiment, a voltage regulator on a memory die is enabled upon receipt of a memory operation. The illustrative voltage regulator includes an analog controller that controls a shunt current based on a current output voltage of the voltage regulator. The illustrative voltage regulator also includes a digital controller that controls several switches based on the input voltage that control an effective resistance of part of the voltage regulator.
    Type: Application
    Filed: September 22, 2021
    Publication date: March 23, 2023
    Applicant: Intel Corporation
    Inventors: Veeresh Garag, Bharat V. Chauhan
  • ENCODED ON-DIE TERMINATION FOR EFFICIENT MULTIPACKAGE TERMINATION
    Publication number: 20210175887
    Abstract: On-die termination (ODT) is triggered through a serial signal encoding on an ODT signal line instead of a simple binary enable signal. An ODT circuit applies one of multiple termination impedances based on the ODT signal encoding. An ODT enable signal line receives an ODT enable signal as multiple serial bits to encode the selected termination impedance, to cause the ODT circuit to apply the selected termination impedance.
    Type: Application
    Filed: December 14, 2020
    Publication date: June 10, 2021
    Inventors: Sheldon G. HIEMSTRA, Veeresh GARAG