Patents by Inventor Veeresh V. Deshpande
Veeresh V. Deshpande has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11521055Abstract: An integrated optical circuit for an optical neural network is provided. The integrated optical circuit is configured to process a phase-encoded optical input signal and to provide a phase-encoded output signal depending on the phase-encoded optical input signal. The phase-encoded output signal emulates a synapse functionality with respect to the phase-encoded optical input signal. A related method and a related design structure are further provided.Type: GrantFiled: April 14, 2018Date of Patent: December 6, 2022Assignee: International Business Machines CorporationInventors: Stefan Abel, Veeresh V. Deshpande, Jean Fompeyrine
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Patent number: 11157807Abstract: An integrated optical circuit for an optical neural network is provided. The optical circuit is configured to process a plurality of phase-encoded optical input signals and to provide a phase-encoded optical output signal depending on the phase-encoded optical input signals. The phase-encoded optical output signal emulates a neuron functionality with respect to the plurality of phase-encoded optical input signals. Such an embodied optical circuit uses the phase to encode information in the optical domain. A related method and a related design structure are further provided.Type: GrantFiled: April 14, 2018Date of Patent: October 26, 2021Assignee: International Business Machines CorporationInventors: Stefan Abel, Veeresh V. Deshpande, Jean Fompeyrine
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Patent number: 10657440Abstract: A neuromorphic network includes a first node configured to transmit a first optical signal and a second node configured to transmit a second optical signal. A waveguide optically connects the first node to the second node. An integrated optical synapse is located on the waveguide between the first node and the second node, the optical synapse configured to change an optical property based on the first optical signal and the second optical signal such that if a correlation between the first optical signal and the second optical signal is strong, the optical connection between the first node and the second node is increased and if the correlation between the first optical signal and the second optical signal is weak, the optical connection between the first node and the second node is decreased.Type: GrantFiled: October 26, 2015Date of Patent: May 19, 2020Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Stefan Abel, Lukas Czomomaz, Veeresh V. Deshpande, Jean Fompeyrine
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Patent number: 10546992Abstract: Embodiments are directed to a superconducting microwave circuit. The circuit includes a substrate and two electrodes. The latter form an electrode pair dimensioned so as to support an electromagnetic field, which allows the circuit to be operated in the microwave domain. The substrate exhibits a raised portion, which includes a top surface and two lateral surfaces. The top surface connects the two lateral surfaces, which show respective undercuts (on the lateral sides of the raised portions). Each of the electrodes includes a structure that includes a potentially superconducting material. Two protruding structures are accordingly formed, which are shaped complementarily to the respective undercuts. This way, the shaped structure of each of the electrodes protrudes toward the other one of the electrodes of the pair.Type: GrantFiled: June 28, 2018Date of Patent: January 28, 2020Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Andreas Fuhrer, Andreas Kuhlmann, Ute Drechsler, Veeresh V. Deshpande, Stefan Filipp, Marc Ganzhorn
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Patent number: 10529771Abstract: A method of fabrication of an array of optoelectronic structures includes first providing a crystalline substrate having cells corresponding to individual optoelectronic structures to be obtained. Each of the cells includes an opening to the substrate. Then, several first layer portions of a first compound semiconductor material are grown in each the opening to at least partly fill a respective one of the cells and form an essentially planar film portion therein. Next, several second layer portions of a second compound semiconductor material are grown over the first layer portions that coalesce to form a coalescent film extending over the first layer portions. Finally, excess portions of materials are removed, to obtain the array of optoelectronic structures. Each optoelectronic structure comprises a stack protruding from the substrate of: a residual portion of one of the second layer portions; and a residual portion of one of the first layer portions.Type: GrantFiled: February 27, 2018Date of Patent: January 7, 2020Assignee: International Business Machines CorporationInventors: Mattias B. Borg, Lukas Czornomaz, Veeresh V. Deshpande, Vladimir Djara, Heike E. Riel, Heinz Schmid
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Publication number: 20200006619Abstract: Embodiments are directed to a superconducting microwave circuit. The circuit includes a substrate and two electrodes. The latter form an electrode pair dimensioned so as to support an electromagnetic field, which allows the circuit to be operated in the microwave domain. The substrate exhibits a raised portion, which includes a top surface and two lateral surfaces. The top surface connects the two lateral surfaces, which show respective undercuts (on the lateral sides of the raised portions). Each of the electrodes includes a structure that includes a potentially superconducting material. Two protruding structures are accordingly formed, which are shaped complementarily to the respective undercuts. This way, the shaped structure of each of the electrodes protrudes toward the other one of the electrodes of the pair.Type: ApplicationFiled: June 28, 2018Publication date: January 2, 2020Inventors: Andreas FUHRER, Andreas KUHLMANN, Ute DRECHSLER, Veeresh V. DESHPANDE, Stefan FILIPP, Marc GANZHORN
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Publication number: 20190318233Abstract: An integrated optical circuit for an optical neural network is provided. The integrated optical circuit is configured to process a phase-encoded optical input signal and to provide a phase-encoded output signal depending on the phase-encoded optical input signal. The phase-encoded output signal emulates a synapse functionality with respect to the phase-encoded optical input signal. A related method and a related design structure are further provided.Type: ApplicationFiled: April 14, 2018Publication date: October 17, 2019Inventors: Stefan Abel, Veeresh V. Deshpande, Jean Fompeyrine
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Publication number: 20190318234Abstract: An integrated optical circuit for an optical neural network is provided. The optical circuit is configured to process a plurality of phase-encoded optical input signals and to provide a phase-encoded optical output signal depending on the phase-encoded optical input signals. The phase-encoded optical output signal emulates a neuron functionality with respect to the plurality of phase-encoded optical input signals. Such an embodied optical circuit uses the phase to encode information in the optical domain. A related method and a related design structure are further provided.Type: ApplicationFiled: April 14, 2018Publication date: October 17, 2019Inventors: Stefan Abel, Veeresh V. Deshpande, Jean Fompeyrine
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Patent number: 10410926Abstract: The invention relates to a method comprising providing a substrate with a channel layer, forming a gate stack structure on the channel layer and forming a raised source and a raised drain on the channel layer. The method further comprises depositing in a non-conformal way an oxide layer above the gate stack structure, the raised source and the raised drain. A first void above the raised source and a second void above the raised drain gate are created adjacent to vertical edges of the gate stack structure. The method further comprises etching the oxide layer for a predefined etching time, thereby removing the oxide layer above the raised source and the raised drain, while keeping it at least partly on the channel layer. Contacts are formed to the raised source and the raised drain. The invention also concerns a corresponding computer program product.Type: GrantFiled: February 1, 2018Date of Patent: September 10, 2019Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Lukas Czornomaz, Veeresh V. Deshpande, Vladimir Djara, Pouya Hashemi
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Patent number: 10395168Abstract: A reservoir computing neuromorphic network includes an input layer comprising one or more input nodes, a reservoir layer comprising a plurality of reservoir nodes, and an output layer comprising one or more output nodes. A portion of at least one of the input layer, the reservoir layer, and the output layer includes an optically tunable material.Type: GrantFiled: October 26, 2015Date of Patent: August 27, 2019Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Stefan Abel, Lukas Czomomaz, Veeresh V. Deshpande, Jean Fompeyrine
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Patent number: 10304934Abstract: The invention relates to a method for forming a field effect transistor. The method comprises providing a substrate with a channel layer, forming a gate stack structure on the channel layer, forming first sidewall spacers, forming a raised source and a raised drain on the channel layer and forming second sidewall spacers above the raised source and the raised drain. The method further includes depositing in a an insulating dielectric layer above the gate stack structure, the first sidewall spacers and the second sidewall spacers, planarization of the insulating dielectric layer and selectively etching the second sidewall spacers. Thereby contact cavities are created on the raised source and the raised drain. The method further includes forming a source contact and a drain contact by filling the contact cavities. The invention also concerns a corresponding computer program product.Type: GrantFiled: August 10, 2018Date of Patent: May 28, 2019Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Lukas Czornomaz, Veeresh V. Deshpande, Vladimir Djara
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Patent number: 10254642Abstract: Various embodiments include approaches for modifying a design layer of an integrated circuit (IC). In some cases, an approach includes: identifying at least one empty region in a design layer used to form the IC; determining whether the at least one empty region requires a fill object; placing at least one fill object in the at least one empty region and tagging the at least one fill object in response to determining the at least one empty region requires a fill object; performing a simplified optical proximity correction (OPC) on the tagged at least one fill object and a complete OPC on the design layer; and generating a modified design layer including a corrected version of the design layer and modified fill objects after the performing of the simplified OPC on the tagged at least one fill object and the complete OPC on the design layer.Type: GrantFiled: January 31, 2018Date of Patent: April 9, 2019Assignee: International Business Machines CorporationInventors: Veeresh V. Deshpande, Howard S. Landis, Arun Sankar Mampazhy, Neelima Mandloi
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Publication number: 20180350925Abstract: The invention relates to a method for forming a field effect transistor. The method comprises providing a substrate with a channel layer, forming a gate stack structure on the channel layer, forming first sidewall spacers, forming a raised source and a raised drain on the channel layer and forming second sidewall spacers above the raised source and the raised drain. The method further includes depositing in a an insulating dielectric layer above the gate stack structure, the first sidewall spacers and the second sidewall spacers, planarization of the insulating dielectric layer and selectively etching the second sidewall spacers. Thereby contact cavities are created on the raised source and the raised drain. The method further includes forming a source contact and a drain contact by filling the contact cavities. The invention also concerns a corresponding computer program product.Type: ApplicationFiled: August 10, 2018Publication date: December 6, 2018Inventors: Lukas Czornomaz, Veeresh V. Deshpande, Vladimir Djara
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Patent number: 10103234Abstract: The invention relates to a method for forming a field effect transistor. The method comprises providing a substrate with a channel layer, forming a gate stack structure on the channel layer, forming first sidewall spacers, forming a raised source and a raised drain on the channel layer and forming second sidewall spacers above the raised source and the raised drain. The method further includes depositing in a an insulating dielectric layer above the gate stack structure, the first sidewall spacers and the second sidewall spacers, planarization of the insulating dielectric layer and selectively etching the second sidewall spacers. Thereby contact cavities are created on the raised source and the raised drain. The method further includes forming a source contact and a drain contact by filling the contact cavities. The invention also concerns a corresponding computer program product.Type: GrantFiled: November 1, 2017Date of Patent: October 16, 2018Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Lukas Czornomaz, Veeresh V. Deshpande, Vladimir Djara
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Publication number: 20180294338Abstract: The invention relates to a method for forming a field effect transistor. The method comprises providing a substrate with a channel layer, forming a gate stack structure on the channel layer, forming first sidewall spacers, forming a raised source and a raised drain on the channel layer and forming second sidewall spacers above the raised source and the raised drain. The method further includes depositing in a an insulating dielectric layer above the gate stack structure, the first sidewall spacers and the second sidewall spacers, planarization of the insulating dielectric layer and selectively etching the second sidewall spacers. Thereby contact cavities are created on the raised source and the raised drain. The method further includes forming a source contact and a drain contact by filling the contact cavities. The invention also concerns a corresponding computer program product.Type: ApplicationFiled: November 1, 2017Publication date: October 11, 2018Inventors: Lukas Czornomaz, Veeresh V. Deshpande, Vladimir Djara
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Publication number: 20180294193Abstract: The invention relates to a method comprising providing a substrate with a channel layer, forming a gate stack structure on the channel layer and forming a raised source and a raised drain on the channel layer. The method further comprises depositing in a non-conformal way an oxide layer above the gate stack structure, the raised source and the raised drain. A first void above the raised source and a second void above the raised drain gate are created adjacent to vertical edges of the gate stack structure. The method further comprises etching the oxide layer for a predefined etching time, thereby removing the oxide layer above the raised source and the raised drain, while keeping it at least partly on the channel layer. Contacts are formed to the raised source and the raised drain. The invention also concerns a corresponding computer program product.Type: ApplicationFiled: February 1, 2018Publication date: October 11, 2018Inventors: Lukas Czornomaz, Veeresh V. Deshpande, Vladimir Djara, Pouya Hashemi
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Publication number: 20180190693Abstract: A method of fabrication of an array of optoelectronic structures includes first providing a crystalline substrate having cells corresponding to individual optoelectronic structures to be obtained. Each of the cells includes an opening to the substrate. Then, several first layer portions of a first compound semiconductor material are grown in each the opening to at least partly fill a respective one of the cells and form an essentially planar film portion therein. Next, several second layer portions of a second compound semiconductor material are grown over the first layer portions that coalesce to form a coalescent film extending over the first layer portions. Finally, excess portions of materials are removed, to obtain the array of optoelectronic structures. Each optoelectronic structure comprises a stack protruding from the substrate of: a residual portion of one of the second layer portions; and a residual portion of one of the first layer portions.Type: ApplicationFiled: February 27, 2018Publication date: July 5, 2018Inventors: Mattias B. Borg, Lukas Czornomaz, Veeresh V. Deshpande, Vladimir Djara, Heike E. Riel, Heinz Schmid
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Publication number: 20180180989Abstract: Various embodiments include approaches for modifying a design layer of an integrated circuit (IC). In some cases, an approach includes: identifying at least one empty region in a design layer used to form the IC; determining whether the at least one empty region requires a fill object; placing at least one fill object in the at least one empty region and tagging the at least one fill object in response to determining the at least one empty region requires a fill object; performing a simplified optical proximity correction (OPC) on the tagged at least one fill object and a complete OPC on the design layer; and generating a modified design layer including a corrected version of the design layer and modified fill objects after the performing of the simplified OPC on the tagged at least one fill object and the complete OPC on the design layer.Type: ApplicationFiled: January 31, 2018Publication date: June 28, 2018Inventors: Veeresh V. Deshpande, Howard S. Landis, Arun Sankar Mampazhy, Neelima Mandloi
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Patent number: 9997409Abstract: The invention relates to a method comprising providing a substrate with a channel layer, forming a gate stack structure on the channel layer and forming a raised source and a raised drain on the channel layer. The method further comprises depositing in a non-conformal way an oxide layer above the gate stack structure, the raised source and the raised drain. A first void above the raised source and a second void above the raised drain gate are created adjacent to vertical edges of the gate stack structure. The method further comprises etching the oxide layer for a predefined etching time, thereby removing the oxide layer above the raised source and the raised drain, while keeping it at least partly on the channel layer. Contacts are formed to the raised source and the raised drain. The invention also concerns a corresponding computer program product.Type: GrantFiled: April 7, 2017Date of Patent: June 12, 2018Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Lukas Czornomaz, Veeresh V. Deshpande, Vladimir Djara, Pouya Hashemi
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Patent number: 9984929Abstract: The invention relates to a method comprising providing a substrate with a channel layer, forming a gate stack structure on the channel layer and forming a raised source and a raised drain on the channel layer. The method further comprises depositing in a non-conformal way an oxide layer above the gate stack structure, the raised source and the raised drain. A first void above the raised source and a second void above the raised drain gate are created adjacent to vertical edges of the gate stack structure. The method further comprises etching the oxide layer for a predefined etching time, thereby removing the oxide layer above the raised source and the raised drain, while keeping it at least partly on the channel layer. Contacts are formed to the raised source and the raised drain. The invention also concerns a corresponding computer program product.Type: GrantFiled: November 1, 2017Date of Patent: May 29, 2018Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Lukas Czornomaz, Veeresh V. Deshpande, Vladimir Djara, Pouya Hashemi