Abstract: A serial, half-duplex start/stop event detection circuit comprises a stop detection flip-flop clocked by a serial data input that takes a serial clock input as an input and generates a stop signal output indicative of a stop event. A start detection flip-flop, clocked by an inverted copy of the serial data input, takes the serial clock input as an input and generates a start signal output indicative of a start event. A first buffer flip-flop, clocked by an inverted copy of the serial clock input, takes the start signal output as an input and generates a first delayed start signal output. Similarly, a second buffer flip-flop, clocked by the serial clock input, takes the first delayed start signal output as an input and generates a second delayed start signal output. The second delayed start signal output resets at least one of said stop detection, start detection or first buffer flip-flops.