Patents by Inventor Vegneswary RAMALINGAM

Vegneswary RAMALINGAM has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240079283
    Abstract: A semiconductor assembly device is provided including a metal layer, a first metal plate, a second metal plate, a metal pillar, an encapsulant, and a die structure having a first terminal and a second terminal, the first terminal of the die structure is in electrically contact with the metal layer, the metal pillar is in electrical contact with the metal layer, and the second terminal of the die is in contact with the first metal plate and the metal pillar is in contact with the second metal plate and where between the die and the metal pillar and between the first metal plate and the second metal plate the encapsulant is provided, and at least one of the metal layer, the first metal plate or the second metal plate are made of a sintered metal powder. The disclosure also pertains to a method for manufacturing such semiconductor assembly device.
    Type: Application
    Filed: August 31, 2023
    Publication date: March 7, 2024
    Applicant: NEXPERIA B.V.
    Inventor: Vegneswary Ramalingam
  • Patent number: 11233003
    Abstract: This disclosure relates to a semiconductor device and method of manufacture, including: a semiconductor die having a first major surface and a first contact terminal arranged thereon and an opposing second major having a second contact terminal arranged thereon and a first lead frame having first and second opposing major surfaces. The first major surface is fixedly attached to the first contact terminal of the semiconductor die. A second lead frame has first and second opposing major surfaces and the first major surface is fixedly attached to the second contact terminal of the semiconductor die. The first lead frame includes an integrally formed external contact portion extending from the first major surface thereof to a plane substantially co-planar with the second major surface of the second leadframe.
    Type: Grant
    Filed: February 11, 2020
    Date of Patent: January 25, 2022
    Assignee: Nexperia B.V.
    Inventors: Christine Ting, Vegneswary Ramalingam, Melvin Hung
  • Publication number: 20220020670
    Abstract: A semiconductor device is provided that includes a frontside and a backside, four sidewalls, a first solder/glue connection on the frontside and a second solder/glue connection on the backside. The semiconductor device is either connected as a chip scale package to a printed circuit board or inside a semiconductor package via one of the four sidewalls, so that the first solder/glue connection and the second solder/glue connection are visible for a visual solder/glue inspection.
    Type: Application
    Filed: July 20, 2021
    Publication date: January 20, 2022
    Applicant: NEXPERIA B.V.
    Inventors: Hartmut Bünning, Hans-Juergen Funke, Stefan Berglund, Justin Y.H. Tan, Vegneswary Ramalingam, Roelf Groenhuis, Joep Stokkermans, Thijs Kniknie
  • Publication number: 20220020679
    Abstract: A semiconductor device is provided that includes a substrate, a pocket within the substrate, a solderable/glueable re-distribution layer arranged in the pocket and a die. The die is arranged downwards, so that a base contact and an emitter contact of the die face the bottom of the device, and a collector contact of the die faces the top of the device. The solderable/glueable re-distribution layer includes a first and second re-distribution layer part and the first re-distribution layer part and the second re-distribution layer part are isolated from each other by an isolating material. The emitter contact is connected to the first re-distribution layer part and the base contact is connected to the second re-distribution layer part. The emitter contacts via the first re-distribution layer part, the base contacts via the second re-distribution layer part, and the collector contact are fan out to the top surface of the semiconductor device.
    Type: Application
    Filed: July 20, 2021
    Publication date: January 20, 2022
    Applicant: NEXPERIA B.V.
    Inventors: Hartmut Bünning, Hans-Juergen Funke, Stefan Berglund, Justin Y.H. Tan, Vegneswary Ramalingam, Roelf Groenhuis, Joep Stokkermans, Thijs Kniknie
  • Publication number: 20200258829
    Abstract: This disclosure relates to a semiconductor device and method of manufacture, including: a semiconductor die having a first major surface and a first contact terminal arranged thereon and an opposing second major having a second contact terminal arranged thereon and a first lead frame having first and second opposing major surfaces. The first major surface is fixedly attached to the first contact terminal of the semiconductor die. A second lead frame has first and second opposing major surfaces and the first major surface is fixedly attached to the second contact terminal of the semiconductor die. The first lead frame includes an integrally formed external contact portion extending from the first major surface thereof to a plane substantially co-planar with the second major surface of the second leadframe.
    Type: Application
    Filed: February 11, 2020
    Publication date: August 13, 2020
    Applicant: NEXPERIA B.V.
    Inventors: Christine TING, Vegneswary RAMALINGAM, Melvin HUNG