Abstract: An automatic cable equalizer (10) is implemented in CMOS technology with a reduced requirement for off-chip components. A continuously-variable gain control resistor (28) of an AGC circuit (12) in a gain section and two additional continuously-variable gain control resistors (76, 82) in a shaping section (16) of the equalizer are driven by monotonically related control voltages (V.sub.H1, V.sub.H2, V.sub.L1, V.sub.L2) which are derived from a single feedback loop section (16) by the use of an inverter (102) and a pair of inverters with voltage offset (104, 105). An arrangement is disclosed for realizing a detector (96) and a filter (98) of the gain control feedback section. Another arrangement (134) is disclosed for realizing the inverter (102) and the inverters with voltage offset (104, 105). A third arrangement (154) is disclosed for realizing gain control resistor networks which include the gain control resistors.

Abstract: A fully differential CMOS operational amplifier (10) of the folded cascode type has a differential input network (12) and a transimpedance stage (14). The transimpedance output stage (14) is made up of two similar negative and positive signal branches (32,34) connected in parallel with each other between supply voltage nodes (V+,V-). Each signal branch includes a P-channel current source transistor (48,60), a cascode transistor (50,62), an N-channel a pull-down transistor (40,52), and an N-channel current source transistor (42,54), all connected in tandem, respectively, between a positive supply voltage node and the drain of a feedback transistor (44,56), which has its source connected to a negative supply voltage node. The drains of the feedback transistors of the two branches are joined.

Abstract: A transconductance circuit (10) has its signal input terminals (28,40) at the gates of a pairs of MOSFETS (16,22; 32,38) which are forced to operate in the triode mode. The outputs of the triode mode MOSFET pair are fed to a cascode transistor (18,20; 34,36) for treatment as a differential signal. The differential output (30,42) of the cascode transistors is highly linear with respect to the input signal at the gates of the triode mode transistors. Bias voltages for the gates of the cascode transistors are generated by a bias network (14). The transconductance circuit 12 includes a cross-coupled set of compensation capacitors (62, 64; 66, 68) formed from devices with the same geometries as the triode mode transistors to compensate for high frequency loss due to the Miller effect in the input transistors.

Abstract: A fully differential CMOS operational amplifier (10) of the folded cascode type includes two similar signal current branches (32,34) connected in parallel between two supply voltage nodes (V+,V-). Each branch includes an N-type bias current transistor (42,54), a P-type cascode transistor (50,62), an N-type pull-down transistor (40,52), and a P-type current source transistor (48,60), all connected respectively in series between the drain of an N-type common mode suppression feedback transistor (44,56) and the drain of a P-type common mode suppression feedback transistor (46,58). The N-type feedback transistor has its source connected to a negative supply voltage node. The P-type feedback transistor has its source connected to a positive supply voltage node. The gates of the feedback transistors of each branch are connected to the output node (36,38) at the drain of the cascode transistor. The gates of the other transistors are supplied with appropriate reference voltages (V.sub.B1, V.sub.B2, V.sub.B3, V.sub.

Abstract: An MOS differential input stage circuit (10) includes first (M1) and second (M2) differential input transistors with input nodes at their gates and output nodes at their drains. The sources are connected to a first current source (24). A second pair of differential transistors (M3,M4) which have their sources connected to a second current source (28), their drains connected to a reference voltage node, and their gates common to the respective first differential input transistors, have their bulk regions in common with the bulk regions (20) of the first differential transistors for isolation from supply voltage noise and from common mode input signal effects.

Abstract: A switched capacitor MOS high-pass filter (10) includes a blocking capacitor (C.sub.1) which accepts an input signal at one side (IN). A first electronic toggle switch (S.sub.1) connects the gate of a depletion-mode buffer transistor (T.sub.1) alternately to the other side of the blocking capacitor (C.sub.1) and to ground in response to a pair of non-overlapping switching pulse trains (.phi..sub.1), (.phi..sub.2). A depletion-mode transistor (T.sub.2) provides current to the buffer transistor (T.sub.1). One side of an output capacitor (C.sub.2) is connected to the source of the buffer transistor (T.sub.1). A second toggle switch (S.sub.2) connects the other side of the output capacitor (C.sub.2) alternately to an output terminal (OUT) and to ground.Also disclosed is a filter (14) which includes a correction network (18) to eliminate from the output signal the effect of a feed-through error voltage generated by the action of the first switch (S.sub.1).

Abstract: Amplifier gain is varied in response to a control voltage by a switched capacitor variable transconductance feedback network. First and second capacitors are connected in series between the input and the output of an operational amplifier. The input side of the first capacitor is switched by a first toggle switch between the input and ground. The output side of the second capacitor is switched by a second toggle switch between the output side and ground. Both toggle switches are operated by a pair of non-overlapping pulse trains. A voltage-controlled variable resistance network is connected between the common node of the capacitors and ground.

Abstract: A high performance operational amplifier 12 circuit 10 nulls the offset voltage by means of switched capacitors (C.sub.2, C.sub.3) and holds the signal output 18 during the nulling. Switching is in response to two non-overlapping pulse trains .phi..sub.1, .phi..sub.2. During an output valid phase .phi..sub.1, with the signal input source connected to the inverting input 14 of the amplifier 12, an offset voltage storage capacitor C.sub.2 is connected between the non-inverting input 16 and ground. A signal storage capacitor C.sub.3 is connected between the output 18 and ground. During a nulling phase .phi..sub.2, the signal storage capacitor C.sub.3 is disconnected from ground and connected between the output 18 and the inverting input 14. The previously grounded side of the offset voltage storage capacitor C.sub.2 is switched to the inverting input port 14. The non-inverting input port 16 is grounded. The offset storage capacitor C.sub.

Abstract: In an NMOS integrated circuit (10), a basic Pierce-type oscillator stage (16) which includes an inverter stage with a quartz crystal resonator (34) is coupled to a transistor-transistor logic output stage (22) through a comparator (18) and a level shifter (20) to achieve a circuit having the combination of a relatively high tolerance to parasitic capacitances and resistances and a well-controlled output duty cycle of nearly 50 percent.

Abstract: A differential input stage is connected to a push-pull output stage with a complementary MOS output pair (30, 32) in a common-source configuration. The gates of the output transistors (30, 32) are each driven by the output of one of a pair of auxiliary transistors (38, 42) which have their gates coupled to the signal. A separate bias current source (41, 44) is connected between the output of each of the auxiliary transistors and a supply node (26). The bias current sources (41, 44) draw current in proportion to the ratio of the transconductances of the auxiliary drive transistors (42, 38) for establishing the voltage across a coupling resistor (36) connecting the output transistor (30, 32) gates and thereby determining the crossover current of the output stage (50). Also disclosed is a frequency response compensation network circuit section (74) which is phase-inverting and provides a local negative feedback loop for the tandem arrangement of intermediate stage (48) and the output stage (50).

Abstract: A compact, complementary metal-oxide on silicon integrated circuit operational amplifier (10, 70, 76) having a differential input stage and an output transistor (50) which has its bias current supplied by a complementary current source transistor (48) also includes filter means for coupling signals from the input stage to the gate (52) of the bias transistor (48). By these means, this normally relatively constant current is increased under certain signal conditions to increase the settling speed. In one form, the filter is a capacitor (64). In another form, it is a parallel combination of a capacitor (64) and a coupling transistor (72) in parallel. The capacitor (64) passes high frequencies, and the resistor (72) passes large amplitude signals. To prevent the signal coupling to the gate (52) from affecting other bias conditions in the circuit, the coupled portion of the gate is isolated from a bias control node (42) by a barrier device (66) which passes only D.C.

Abstract: An internally compensated monolithic integrated operational amplifier circuit has a differential input stage, balanced complementary common base stage, a complementary compound emitter-follower stage, and a push-pull output stage. The push-pull output stage includes complementary common emitter transistors, the base electrode of each transistor connected to a transistor connected in common base configuration. Bandwidth and slew rate are enhanced by a feed-forward capacitor connected between the amplifier inverting input and the input to the push-pull output stage and also by a range extender network connected between the output of the input differential stage and the input of the push-pull output stage. Internal bias voltages are referenced to the potential applied to the amplifier noninverting input by means of a voltage follower circuit which is interactively connected with a diode chain and current sources.

Abstract: An integrated circuit digital-to-analog converter circuit of the binary weighted current summing type in which the emitter potentials of the transistor current sources are maintained substantially equal by controlling the voltage differential between the base electrodes of the current source transistors. In one disclosed embodiment, the base electrodes of the transistor current sources are connected to a resistive divider network and the voltage across each of the resistors is maintained substantially equal to (kT/q) ln 2. The disclosed circuit can be used as an alternative to, or in combination with, prior art emitter-scaling techniques.