Patents by Inventor Veit Klee
Veit Klee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7985676Abstract: To form a semiconductor device, an insulating layer is formed over a conductive region and a pattern transfer layer is formed over the insulating layer. The pattern transfer layer is patterned in the reverse tone of a layout of recesses to be formed in the insulating layer such that the pattern transfer layer remains over regions where the recesses are to be formed. A mask material is formed over the insulating layer and is aligned with the pattern transfer layer. Remaining portions of the pattern transfer layer are removed and recesses are etched in the insulating layer using the mask material as a mask.Type: GrantFiled: January 25, 2010Date of Patent: July 26, 2011Assignee: Infineon Technologies AGInventors: Veit Klee, Roman Knoefler, Uwe Paul Schroeder
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Publication number: 20100124820Abstract: To form a semiconductor device, an insulating layer is formed over a conductive region and a pattern transfer layer is formed over the insulating layer. The pattern transfer layer is patterned in the reverse tone of a layout of recesses to be formed in the insulating layer such that the pattern transfer layer remains over regions where the recesses are to be formed. A mask material is formed over the insulating layer and is aligned with the pattern transfer layer. Remaining portions of the pattern transfer layer are removed and recesses are etched in the insulating layer using the mask material as a mask.Type: ApplicationFiled: January 25, 2010Publication date: May 20, 2010Inventors: Veit Klee, Roman Knoefler, Uwe Paul Schroeder
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Patent number: 7678704Abstract: To form a semiconductor device, an insulating layer is formed over a conductive region and a pattern transfer layer is formed over the insulating layer. The pattern transfer layer is patterned in the reverse tone of a layout of recesses to be formed in the insulating layer such that the pattern transfer layer remains over regions where the recesses are to be formed. A mask material is formed over the insulating layer and is aligned with the pattern transfer layer. Remaining portions of the pattern transfer layer are removed and recesses are etched in the insulating layer using the mask material as a mask.Type: GrantFiled: December 13, 2005Date of Patent: March 16, 2010Assignee: Infineon Technologies AGInventors: Veit Klee, Roman Knoefler, Uwe Paul Schroeder
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Patent number: 7235472Abstract: A method of making a semiconductor device for an integrated circuit chip. An interim gate electrode stack formed includes a top silicon portion patterned from a second silicon layer, a sandwiched oxide portion patterned from an etch stop oxide layer, and a bottom silicon portion patterned from a first silicon layer formed on a gate dielectric layer over a substrate. Etching the second silicon layer is stopped at the etch stop oxide layer. A spacer structure is formed about the interim gate electrode stack, and then the top silicon portion and the sandwiched oxide portion are removed. The spacer structure height may be reduced. A metal layer is formed over the bottom silicon portion of the interim gate electrode stack and over source and drain regions of the substrate, all of which are silicided at the same time to form a fully silicided (FUSI) gate electrode and silicided source and drain regions.Type: GrantFiled: November 12, 2004Date of Patent: June 26, 2007Assignee: Infineon Technologies AGInventors: Veit Klee, Sun-Oo Kim
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Publication number: 20070134909Abstract: To form a semiconductor device, an insulating layer is formed over a conductive region and a pattern transfer layer is formed over the insulating layer. The pattern transfer layer is patterned in the reverse tone of a layout of recesses to be formed in the insulating layer such that the pattern transfer layer remains over regions where the recesses are to be formed. A mask material is formed over the insulating layer and is aligned with the pattern transfer layer. Remaining portions of the pattern transfer layer are removed and recesses are etched in the insulating layer using the mask material as a mask.Type: ApplicationFiled: December 13, 2005Publication date: June 14, 2007Inventors: Veit Klee, Roman Knoefler, Uwe Schroeder
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Publication number: 20060105557Abstract: A method of making a semiconductor device for an integrated circuit chip. An interim gate electrode stack formed includes a top silicon portion patterned from a second silicon layer, a sandwiched oxide portion patterned from an etch stop oxide layer, and a bottom silicon portion patterned from a first silicon layer formed on a gate dielectric layer over a substrate. Etching the second silicon layer is stopped at the etch stop oxide layer. A spacer structure is formed about the interim gate electrode stack, and then the top silicon portion and the sandwiched oxide portion are removed. The spacer structure height may be reduced. A metal layer is formed over the bottom silicon portion of the interim gate electrode stack and over source and drain regions of the substrate, all of which are silicided at the same time to form a fully silicided (FUSI) gate electrode and silicided source and drain regions.Type: ApplicationFiled: November 12, 2004Publication date: May 18, 2006Inventors: Veit Klee, Sun-Oo Kim
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Publication number: 20040058550Abstract: Disclosed is an optical lithographic mask having one or more dummy patterns, each said dummy pattern having a masked area of said optical lithographic mask separated from one or more feature masked areas on said optical lithographic mask by an unmasked region of width d, wherein said width d is selected to substantially minimize an average deviation between the dimensions of said feature masked areas and corresponding features etched out upon a semiconductor surface utilizing said optical lithographic mask.Type: ApplicationFiled: September 19, 2002Publication date: March 25, 2004Applicant: Infineon Technologies North America Corp.Inventors: Tobias Mono, Veit Klee, Paul Wensley, Martin Commons
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Patent number: 6605396Abstract: An alternating phase shift mask (400) and method of manufacturing thereof including assist edges (450) and (452) surrounding a main phase edge (420). Assist edges (450) and (452) improve the resolution of the alternating phase shift mask (400), thus enabling the patterning of smaller size features on a semiconductor wafer.Type: GrantFiled: August 6, 2001Date of Patent: August 12, 2003Assignee: Infineon Technologies, AGInventors: Uwe Paul Schroeder, Tobias Mono, Veit Klee
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Patent number: 6566227Abstract: A method of providing shallow trench (143) isolation for a semiconductor wafer (100). Trenches (113) are formed within a first semiconductor material (112) and a pad nitride (114), leaving a portion of first semiconductor material (112) and pad nitride (114) in a region between the trenches (113). A second semiconductor material (116) is deposited over the trenches (113) to fill the trenches (113) to a height below the first semiconductor material (112) top surface. A first insulator (130) is selectively formed over the second semiconductor material (116). The pad nitride (114) and a portion of the first semiconductor material (112) between the trenches (113) are removed to isolate element regions of the wafer (100) and form straps (142) having a low resistance.Type: GrantFiled: August 13, 2001Date of Patent: May 20, 2003Assignee: Infineon Technologies AGInventors: Paul Wensley, Martin Commons, Tobias Mono, Veit Klee
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Patent number: 6551874Abstract: A nitride hard mask (230) is used to isolate active areas of a DRAM cell. The shallow trench isolation (STI) method includes forming memory cells comprising deep trenches (216) on a semiconductor wafer (200). The memory cell deep trenches (216) are separated from active areas (212) by a region of substrate (212). A nitride hard mask (230) is formed over the semiconductor wafer (200). The wafer (200) is patterned with the nitride hard mask (230), and the wafer (200) is etched to remove the region of substrate (212) between the deep trenches and active areas to provide shallow trench isolation. An etch chemistry selective to the nitride hard mask (230) is used.Type: GrantFiled: June 22, 2001Date of Patent: April 22, 2003Assignee: Infineon Technologies, AGInventors: John Pohl, Nirmal Chaudhary, Veit Klee, Tobias Mono, Paul Schroeder
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Publication number: 20030045051Abstract: A nitride hard mask (230) is used to isolate active areas of a DRAM cell. The shallow trench isolation (STI) method includes forming memory cells comprising deep trenches (216) on a semiconductor wafer (200). The memory cell deep trenches (216) are separated from active areas (212) by a region of substrate (212). A nitride hard mask (230) is formed over the semiconductor wafer (200). The wafer (200) is patterned with the nitride hard mask (230), and the wafer (200) is etched to remove the region of substrate (212) between the deep trenches and active areas to provide shallow trench isolation. An etch chemistry selective to the nitride hard mask (230) is used.Type: ApplicationFiled: June 22, 2001Publication date: March 6, 2003Applicant: Infineon Technologies North America Corp.Inventors: John Pohl, Nirmal Chaudhary, Veit Klee, Tobias Mono, Paul Schroeder
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Publication number: 20030032257Abstract: A method of providing shallow trench (143) isolation for a semiconductor wafer (100). Trenches (113) are formed within a first semiconductor material (112) and a pad nitride (114), leaving a portion of first semiconductor material (112) and pad nitride (114) in a region between the trenches (113). A second semiconductor material (116) is deposited over the trenches (113) to fill the trenches (113) to a height below the first semiconductor material (112) top surface. A first insulator (130) is selectively formed over the second semiconductor material (116). The pad nitride (114) and a portion of the first semiconductor material (112) between the trenches (113) are removed to isolate element regions of the wafer (100) and form straps (142) having a low resistance.Type: ApplicationFiled: August 13, 2001Publication date: February 13, 2003Inventors: Paul Wensley, Martin Commons, Tobias Mono, Veit Klee
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Publication number: 20030027057Abstract: An alternating phase shift mask (400) and method of manufacturing thereof including assist edges (450) and (452) surrounding a main phase edge (420). Assist edges (450) and (452) improve the resolution of the alternating phase shift mask (400), thus enabling the patterning of smaller size features on a semiconductor wafer.Type: ApplicationFiled: August 6, 2001Publication date: February 6, 2003Inventors: Uwe Paul Schroeder, Tobias Mono, Veit Klee