Patents by Inventor Velayudhan V. Nair

Velayudhan V. Nair has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Digital-to-analog converter with no offset-induced errors
    Patent number: 4843394
    Abstract: A digital-to-analog converter network for converting a digital signal having a plurality of binary bits into an analog output signal includes an R-2R ladder array (8a), a reference current source (IREF), a plurality of switches (S1, S2, . . . S9) associated with ladder sections of the ladder array (8a), and an operational amplifier (14). An equalization circuit (17) is operatively coupled to the inverting input of the operational amplifier (14) for selectively switching in a code-dependent impedance so that the effective output impedance of the ladder array (8a) remains substantially constant with binary codes of the digital input signal.
    Type: Grant
    Filed: January 21, 1988
    Date of Patent: June 27, 1989
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Alfredo R. Linz, Joe W. Peterson, Velayudhan V. Nair