Patents by Inventor Vencent Chang
Vencent Chang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 9366969Abstract: System and method for enhancing optical lithography methodology for hole patterning in semiconductor fabrication are described. In one embodiment, a photolithography system comprises an illumination system for conditioning light from a light source, the illumination system producing a three-pore illumination pattern; a reticle comprising at least a portion of a pattern to be imaged onto a substrate, wherein the three-pore illumination pattern produced by the illumination system is projected through the reticle; and a projection lens disposed between the reticle and the substrate.Type: GrantFiled: June 21, 2013Date of Patent: June 14, 2016Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chia-Chu Liu, Kuei Shun Chen, Norman Chen, Vencent Chang, Chin-Hsiang Lin
-
Patent number: 9091923Abstract: Contrast enhancing exposure apparatus and method for use in semiconductor fabrication are described. In one embodiment, a method for forming a pattern on a substrate, wherein the substrate includes a photoresist layer comprising photoacid generators (“PAGs”) and photobase generators (“PBGs”), is described.Type: GrantFiled: February 22, 2007Date of Patent: July 28, 2015Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: George Liu, Vencent Chang, Norman Chen, Kuei Shun Chen, Chin-Hsiang Lin
-
Patent number: 8815496Abstract: The method of patterning a photosensitive layer includes providing a substrate including a first layer formed thereon, treating the substrate including the first layer with cations, forming a first photosensitive layer over the first layer, patterning the first photosensitive layer to form a first pattern, treating the first pattern with cations, forming a second photosensitive layer over the treated first pattern, patterning the second photosensitive layer to form a second pattern, and processing the first layer using the first and second patterns as a mask.Type: GrantFiled: February 22, 2013Date of Patent: August 26, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hsiao-Tzu Lu, Kuei Shun Chen, Tsiao-Chen Wu, Vencent Chang, George Liu
-
Patent number: 8623231Abstract: A method for etching an ultra thin film is provided which includes providing a substrate having the ultra thin film formed thereon, patterning a photosensitive layer formed over the ultra thin film, etching the ultra thin film using the patterned photosensitive layer, and removing the patterned photosensitive layer. The etching process includes utilizing an etch material with a diffusion resistant carrier such that the etch material is prevented from diffusing to a region underneath the photosensitive layer and removing portions of the ultra thin film underneath the photosensitive layer.Type: GrantFiled: June 11, 2008Date of Patent: January 7, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: George Liu, Kuei Shun Chen, Vencent Chang, Chih-Yang Yeh
-
Publication number: 20130286371Abstract: System and method for enhancing optical lithography methodology for hole patterning in semiconductor fabrication are described. In one embodiment, a photolithography system comprises an illumination system for conditioning light from a light source, the illumination system producing a three-pore illumination pattern; a reticle comprising at least a portion of a pattern to be imaged onto a substrate, wherein the three-pore illumination pattern produced by the illumination system is projected through the reticle; and a projection lens disposed between the reticle and the substrate.Type: ApplicationFiled: June 21, 2013Publication date: October 31, 2013Inventors: George Liu, Kuei Shun Chen, Norman Chen, Vencent Chang, Chin-Hsiang Lin
-
Patent number: 8472005Abstract: System and method for enhancing optical lithography methodology for hole patterning in semiconductor fabrication are described. In one embodiment, a photolithography system comprises an illumination system for conditioning light from a light source, the illumination system producing a three-pore illumination pattern; a reticle comprising at least a portion of a pattern to be imaged onto a substrate, wherein the three-pore illumination pattern produced by the illumination system is projected through the reticle; and a projection lens disposed between the reticle and the substrate.Type: GrantFiled: February 22, 2007Date of Patent: June 25, 2013Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: George Liu, Kuei Shun Chen, Norman Chen, Vencent Chang, Chin-Hsiang Lin
-
Patent number: 8394576Abstract: The method of patterning a photosensitive layer includes providing a substrate including a first layer formed thereon, treating the substrate including the first layer with cations, forming a first photosensitive layer over the first layer, patterning the first photosensitive layer to form a first pattern, treating the first pattern with cations, forming a second photosensitive layer over the treated first pattern, patterning the second photosensitive layer to form a second pattern, and processing the first layer using the first and second patterns as a mask.Type: GrantFiled: January 10, 2012Date of Patent: March 12, 2013Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hsiao-Tzu Lu, Kuei Shun Chen, Tsiao-Chen Wu, Vencent Chang, George Liu
-
Publication number: 20120114872Abstract: The method of patterning a photosensitive layer includes providing a substrate including a first layer formed thereon, treating the substrate including the first layer with cations, forming a first photosensitive layer over the first layer, patterning the first photosensitive layer to form a first pattern, treating the first pattern with cations, forming a second photosensitive layer over the treated first pattern, patterning the second photosensitive layer to form a second pattern, and processing the first layer using the first and second patterns as a mask.Type: ApplicationFiled: January 10, 2012Publication date: May 10, 2012Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Hsiao-Tzu Lu, Keui Shun Chen, Tsiao-Chen Wu, Vencent Chang, George Liu
-
Patent number: 8124323Abstract: The method of patterning a photosensitive layer includes providing a substrate including a first layer formed thereon, treating the substrate including the first layer with cations, forming a first photosensitive layer over the first layer, patterning the first photosensitive layer to form a first pattern, treating the first pattern with cations, forming a second photosensitive layer over the treated first pattern, patterning the second photosensitive layer to form a second pattern, and processing the first layer using the first and second patterns as a mask.Type: GrantFiled: September 25, 2007Date of Patent: February 28, 2012Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hsiao-Tzu Lu, Keui Shun Chen, Tsiao-Chen Wu, Vencent Chang, George Liu
-
Patent number: 8119533Abstract: Provided is a semiconductor device. The device includes a substrate having a photo acid generator (PAG) layer on the substrate. The PAG layer is exposed to radiation. A photoresist layer is formed on the exposed PAG layer. The exposed PAG layer generates an acid. The acid decomposes a portion of the formed photoresist layer. In one embodiment, the PAG layer includes organic BARC. The decomposed portion of the photoresist layer may be used as a masking element.Type: GrantFiled: December 31, 2009Date of Patent: February 21, 2012Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: George Liu, Kuei Shun Chen, Vencent Chang, Shang-Wen Chang
-
Patent number: 7960821Abstract: An integrated circuit device and method of making the integrated circuit device are disclosed. An exemplary apparatus includes: a semiconductor layer; and a dielectric layer on the semiconductor layer, the dielectric layer having conductive vias and dummy vias formed therein, wherein the conductive vias and dummy vias extend varying distances into the dielectric layer, the conductive vias extending through the dielectric layer to the semiconductor layer, and the dummy vias extending through the dielectric layer to a distance above the semiconductor layer.Type: GrantFiled: March 3, 2010Date of Patent: June 14, 2011Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Kuei Shun Chen, Chin-Hsiang Lin, Vencent Chang, Lawrence Lin, Lai Chien Wen, Jhun Hua Chen
-
Patent number: 7767570Abstract: A method of making an integrated circuit includes providing a low-k dielectric layer on a substrate, the low-k dielectric layer including or adjacent to a plurality of conductive features; patterning the low-k dielectric layer to form trenches; patterning the low-k dielectric layer to form conductive vias and dummy vias, wherein each of the conductive vias is aligned with at least one of the plurality of the conductive features and at least one of the trenches, and each of the dummy vias is a distance above the plurality of conductive features; filling the trenches, conductive vias, and dummy vias using one or more conductive materials; and planarizing the conductive material(s).Type: GrantFiled: July 12, 2006Date of Patent: August 3, 2010Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Kuei Shun Chen, Chin-Hsiang Lin, Vencent Chang, Lawrence Lin, Lai Chien Wen, Jhun Hua Chen
-
Publication number: 20100155963Abstract: An integrated circuit device and method of making the integrated circuit device are disclosed. An exemplary apparatus includes: a semiconductor layer; and a dielectric layer on the semiconductor layer, the dielectric layer having conductive vias and dummy vias formed therein, wherein the conductive vias and dummy vias extend varying distances into the dielectric layer, the conductive vias extending through the dielectric layer to the semiconductor layer, and the dummy vias extending through the dielectric layer to a distance above the semiconductor layer.Type: ApplicationFiled: March 3, 2010Publication date: June 24, 2010Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Kuei Shun Chen, Chin-Hsiang Lin, Vencent Chang, Lawrence Lin, Lai Chien Wen, Jhun Hua Chen
-
Publication number: 20100109054Abstract: Provided is a semiconductor device. The device includes a substrate having a photo acid generator (PAG) layer on the substrate. The PAG layer is exposed to radiation. A photoresist layer is formed on the exposed PAG layer. The exposed PAG layer generates an acid. The acid decomposes a portion of the formed photoresist layer. In one embodiment, the PAG layer includes organic BARC. The decomposed portion of the photoresist layer may be used as a masking element.Type: ApplicationFiled: December 31, 2009Publication date: May 6, 2010Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: George Liu, Kuei Shun Chen, Vencent Chang, Shang-Wen Chang
-
Patent number: 7648918Abstract: Provided is a method of fabricating a semiconductor device. The method includes providing a substrate, forming a photo acid generator (PAG) layer on the substrate, exposing the PAG layer to radiation, and forming a photoresist layer on the exposed PAG layer. The exposed PAG layer generates an acid. The acid decomposes a portion of the formed photoresist layer. In one embodiment, the PAG layer includes organic BARC. The decomposed portion of the photoresist layer may be used as a masking element.Type: GrantFiled: August 20, 2007Date of Patent: January 19, 2010Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: George Liu, Kuei Shun Chen, Vencent Chang, Shang-Wen Chang
-
Patent number: 7642101Abstract: A semiconductor device is fabricated to include one or more sets of calibration patterns used to measure line pitch and line focus.Type: GrantFiled: December 5, 2006Date of Patent: January 5, 2010Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: George Liu, Vencent Chang, Chin-Hsiang Lin, Kuei Shun Chen, Norman Chen
-
Publication number: 20090311628Abstract: A method for etching an ultra thin film is provided which includes providing a substrate having the ultra thin film formed thereon, patterning a photosensitive layer formed over the ultra thin film, etching the ultra thin film using the patterned photosensitive layer, and removing the patterned photosensitive layer. The etching process includes utilizing an etch material with a diffusion resistant carrier such that the etch material is prevented from diffusing to a region underneath the photosensitive layer and removing portions of the ultra thin film underneath the photosensitive layer.Type: ApplicationFiled: June 11, 2008Publication date: December 17, 2009Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: George Liu, Kuei Shun Chen, Vencent Chang, Chih-Yang Yeh
-
Publication number: 20090081591Abstract: The method of patterning a photosensitive layer includes providing a substrate including a first layer formed thereon, treating the substrate including the first layer with cations, forming a first photosensitive layer over the first layer, patterning the first photosensitive layer to form a first pattern, treating the first pattern with cations, forming a second photosensitive layer over the treated first pattern, patterning the second photosensitive layer to form a second pattern, and processing the first layer using the first and second patterns as a mask.Type: ApplicationFiled: September 25, 2007Publication date: March 26, 2009Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Hsiao-Tzu Lu, Keui Shun Chen, Tsiao-Chen Wu, Vencent Chang, George Liu
-
Publication number: 20090053899Abstract: Provided is a method of fabricating a semiconductor device. The method includes providing a substrate, forming a photo acid generator (PAG) layer on the substrate, exposing the PAG layer to radiation, and forming a photoresist layer on the exposed PAG layer. The exposed PAG layer generates an acid. The acid decomposes a portion of the formed photoresist layer. In one embodiment, the PAG layer includes organic BARC. The decomposed portion of the photoresist layer may be used as a masking element.Type: ApplicationFiled: August 20, 2007Publication date: February 26, 2009Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: George Liu, Kuei Shun Chen, Vencent Chang, Shang-Wen Chang
-
Patent number: 7432042Abstract: An immersion lithography process is described as follows. A photoresist layer and a protective layer are sequentially formed on a material layer, and then an immersion exposure step is performed to define an exposed portion and an unexposed portion in the photoresist layer. A solubilization step is conducted to solubilize the protective layer on the exposed portion of the photoresist layer, and then a development step is conducted to remove the exposed portion of the photoresist layer and the protective layer thereon. Since the photoresist layer is covered with the protective layer, the chemicals in the photoresist layer do not diffuse into the immersion liquid to cause contamination. The protective layer can be patterned simultaneously in the development step, and no extra step is required to remove the protective layer. Therefore, the whole lithography process is not complicated.Type: GrantFiled: December 3, 2003Date of Patent: October 7, 2008Assignee: United Microelectronics Corp.Inventors: Vencent Chang, George Liu, Norman Chen