Patents by Inventor Venkat Abilash Reddy Nerallapally

Venkat Abilash Reddy Nerallapally has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Performing testing utilizing staggered clocks
    Patent number: 11668750
    Abstract: During functional/normal operation of an integrated circuit including multiple independent processing elements, a selected independent processing element is taken offline and the functionality of the selected independent processing element is then tested while the remaining independent processing elements continue functional operation. To minimize voltage drops resulting from current fluctuations produced by the testing of the processing element, clocks used to synchronize operations within each partition of a processing element are staggered. This varies the toggle rate within each partition of the processing element during the testing of the processing core, thereby reducing the resulting voltage drop. This may also improve test quality within an automated test equipment (ATE) environment.
    Type: Grant
    Filed: September 17, 2021
    Date of Patent: June 6, 2023
    Assignee: NVIDIA CORPORATION
    Inventors: Sailendra Chadalavada, Venkat Abilash Reddy Nerallapally, Jaison Daniel Kurien, Bonita Bhaskaran, Milind Sonawane, Shantanu Sarangi, Purnabha Majumder
  • PERFORMING TESTING UTILIZING STAGGERED CLOCKS
    Publication number: 20230089800
    Abstract: During functional/normal operation of an integrated circuit including multiple independent processing elements, a selected independent processing element is taken offline and the functionality of the selected independent processing element is then tested while the remaining independent processing elements continue functional operation. To minimize voltage drops resulting from current fluctuations produced by the testing of the processing element, clocks used to synchronize operations within each partition of a processing element are staggered. This varies the toggle rate within each partition of the processing element during the testing of the processing core, thereby reducing the resulting voltage drop. This may also improve test quality within an automated test equipment (ATE) environment.
    Type: Application
    Filed: September 17, 2021
    Publication date: March 23, 2023
    Inventors: Sailendra Chadalavada, Venkat Abilash Reddy Nerallapally, Jaison Daniel Kurien, Bonita Bhaskaran, Milind Sonawane, Shantanu Sarangi, Purnabha Majumder
  • On-chip execution of in-system test utilizing a generalized test image
    Patent number: 10890620
    Abstract: Systems and methods enable the updating of tests, test sequences, fault models, and test conditions such as voltage and clock frequencies, over the life cycle of a safety critical application for complex integrated circuits and systems.
    Type: Grant
    Filed: May 17, 2019
    Date of Patent: January 12, 2021
    Assignee: NVIDIA Corp.
    Inventors: Milind Bhaiyyasaheb Sonawane, Shantanu K. Sarangi, Sailendra Chadalavada, Sumit Raj, Rangavajjula Kameswara Naga Mahesh, Jayesh Kumar Pandey, Venkat Abilash Reddy Nerallapally
  • ON-CHIP EXECUTION OF IN-SYSTEM TEST UTILIZING A GENERALIZED TEST IMAGE
    Publication number: 20200363470
    Abstract: Systems and methods enable the updating of tests, test sequences, fault models, and test conditions such as voltage and clock frequencies, over the life cycle of a safety critical application for complex integrated circuits and systems.
    Type: Application
    Filed: May 17, 2019
    Publication date: November 19, 2020
    Inventors: Milind Bhaiyyasaheb Sonawane, Shantanu K. Sarangi, Sailendra Chadalavada, Sumit Raj, Rangavajjula Kameswara Naga Mahesh, Jayesh Kumar Pandey, Venkat Abilash Reddy Nerallapally
  • Field adaptable in-system test mechanisms
    Patent number: 10746798
    Abstract: A system for testing complex integrated circuits in the field using updated tests, test sequences, models, and test conditions such as voltage and clock frequencies, over the life cycle of the circuit.
    Type: Grant
    Filed: May 31, 2019
    Date of Patent: August 18, 2020
    Assignee: NVIDIA Corp.
    Inventors: Sailendra Chadalavada, Shantanu K. Sarangi, Milind Bhaiyyasaheb Sonawane, Sunil Bhavsar, Jue Wu, Bonita Bhaskaran, Venkat Abilash Reddy Nerallapally, Badrinath Srirangam