Patents by Inventor Venkat Ananthan

Venkat Ananthan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10490644
    Abstract: In a general aspect, a power semiconductor device can include a silicon carbide (SiC) substrate and a SiC epitaxial layer disposed on the SiC substrate. The device can include a well region disposed in the epitaxial layer, a source region disposed in the well region and a gate trench disposed in the epitaxial layer and adjacent to the source region. The gate trench can have a depth that is greater than a depth of the well region and less than a depth of the epitaxial layer. The device can include a hybrid gate dielectric disposed on a sidewall of the gate trench and a bottom surface of the gate trench. The hybrid gate dielectric can include a first high-k material and a second high-k dielectric material that is different than the first high-k dielectric material. The device can include a conductive gate electrode disposed on the hybrid gate dielectric.
    Type: Grant
    Filed: May 17, 2018
    Date of Patent: November 26, 2019
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Salman Akram, Venkat Ananthan
  • Publication number: 20180269302
    Abstract: In a general aspect, a power semiconductor device can include a silicon carbide (SiC) substrate and a SiC epitaxial layer disposed on the SiC substrate. The device can include a well region disposed in the epitaxial layer, a source region disposed in the well region and a gate trench disposed in the epitaxial layer and adjacent to the source region. The gate trench can have a depth that is greater than a depth of the well region and less than a depth of the epitaxial layer. The device can include a hybrid gate dielectric disposed on a sidewall of the gate trench and a bottom surface of the gate trench. The hybrid gate dielectric can include a first high-k material and a second high-k dielectric material that is different than the first high-k dielectric material. The device can include a conductive gate electrode disposed on the hybrid gate dielectric.
    Type: Application
    Filed: May 17, 2018
    Publication date: September 20, 2018
    Applicant: FAIRCHILD SEMICONDUCTOR CORPORATION
    Inventors: Salman AKRAM, Venkat ANANTHAN
  • Patent number: 10002941
    Abstract: In a general aspect, a power semiconductor device can include a silicon carbide (SiC) substrate and a SiC epi-layer disposed on the SiC substrate. The device can also include a first well region, a second well region disposed in the SiC epi-layer, a first source region disposed in the first well region, and a second source region disposed in the second well region. The device can further include a gate structure disposed on the SiC epi-layer and extending between the first source region and the second source region. The gate structure can include a hybrid gate dielectric. The hybrid gate dielectric can include a first high-k dielectric material and a second high-k dielectric material. The device can also include a conductive gate electrode disposed on the hybrid gate dielectric.
    Type: Grant
    Filed: May 18, 2016
    Date of Patent: June 19, 2018
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Salman Akram, Venkat Ananthan
  • Publication number: 20160343823
    Abstract: In a general aspect, a power semiconductor device can include a silicon carbide (SiC) substrate and a SiC epi-layer disposed on the SiC substrate. The device can also include a well region disposed in the SiC epi-layer and a source region disposed in the well region. The device can further include a gate trench disposed in the SiC epi-layer and adjacent to the source region, the gate trench having a depth that is greater than a depth of the well region and is less than a depth of the SiC epi-layer. The device can also include a hybrid gate dielectric disposed on a sidewall of the gate trench and a bottom surface of the gate trench. The hybrid gate dielectric can include a first high-k dielectric material and a second high-k dielectric material. The device can also include a conductive gate electrode disposed on the hybrid gate dielectric.
    Type: Application
    Filed: May 18, 2016
    Publication date: November 24, 2016
    Inventors: Salman AKRAM, Venkat ANANTHAN
  • Patent number: 9443906
    Abstract: Control elements that can be suitable for nonvolatile memory device applications are disclosed. The control element can have low leakage currents at low voltages to reduce sneak current paths for non selected devices, and high leakage currents at high voltages to minimize voltage drops during device switching. The control element can be based on a single dielectric layer or on a multilayer dielectric stack.
    Type: Grant
    Filed: December 20, 2013
    Date of Patent: September 13, 2016
    Assignee: Intermolecular, Inc.
    Inventors: Monica Sawkar Mathur, Venkat Ananthan, Mark Clark, Prashant B. Phatak
  • Patent number: 9397141
    Abstract: Selector devices that can be suitable for memory device applications can have low leakage currents at low voltages to reduce sneak current paths for non selected devices, and high leakage currents at high voltages to minimize voltage drops during device switching. In some embodiments, the selector device can include a first electrode, a tri-layer dielectric layer, and a second electrode. The tri-layer dielectric layer can include a high leakage dielectric layer sandwiched between two lower leakage dielectric layers. The low leakage layers can function to restrict the current flow across the selector device at low voltages. The high leakage dielectric layer can function to enhance the current flow across the selector device at high voltages.
    Type: Grant
    Filed: June 3, 2014
    Date of Patent: July 19, 2016
    Assignee: Intermolecular, Inc.
    Inventors: Imran Hashim, Venkat Ananthan, Tony P. Chiang, Prashant B. Phatak
  • Patent number: 9177998
    Abstract: MIMCAP devices are provided that can be suitable for memory device applications, such as current selector devices for cross point memory array. The MIMCAP devices can have lower thermal budget as compared to Schottky diodes and controllable lower barrier height and lower series resistance as compared to MIMCAP tunneling diodes. The MIMCAP diode can include a low defect dielectric layer, a high defect dielectric layer, sandwiched between two electrodes having different work function values.
    Type: Grant
    Filed: September 19, 2014
    Date of Patent: November 3, 2015
    Assignee: Intermolecular, Inc.
    Inventors: Venkat Ananthan, Imran Hashim, Prashant B. Phatak
  • Publication number: 20150179933
    Abstract: Control elements that can be suitable for nonvolatile memory device applications are disclosed. The control element can have low leakage currents at low voltages to reduce sneak current paths for non selected devices, and high leakage currents at high voltages to minimize voltage drops during device switching. The control element can be based on a single dielectric layer or on a multilayer dielectric stack.
    Type: Application
    Filed: December 20, 2013
    Publication date: June 25, 2015
    Applicant: Intermolecular, Inc.
    Inventors: Monica Sawkar Mathur, Venkat Ananthan, Mark Clark, Prashant B. Phatak
  • Publication number: 20150179934
    Abstract: Control elements that can be suitable for nonvolatile memory device applications are disclosed. The control element can have low leakage currents at low voltages to reduce sneak current paths for non selected devices, and high leakage currents at high voltages to minimize voltage drops during device switching. The control element can be based on multilayer dielectric stacks. The control element can include a zirconium oxide-strontium-titanium oxide-zirconium oxide multilayer stack. The zirconium oxide can be replaced by at least one of hafnium oxide, aluminum oxide, magnesium oxide, or one of the lanthanide oxides.
    Type: Application
    Filed: December 20, 2013
    Publication date: June 25, 2015
    Applicant: Intermolecular, Inc.
    Inventors: Monica Sawkar Mathur, Venkat Ananthan, Prashant B. Phatak
  • Patent number: 9040465
    Abstract: A combination of deposition processes can be used to evaluate layer properties using a combinatorial workflow. The processes can include a base ALD process and another process, such as a PVD process. The high productivity combinatorial technique can provide an evaluation of the material properties for given ALD base layer and PVD additional elements. An ALD process can then be developed to provide the desired layers, replacing the ALD and PVD combination.
    Type: Grant
    Filed: November 19, 2012
    Date of Patent: May 26, 2015
    Assignee: Intermolecular, Inc.
    Inventors: Prashant B Phatak, Venkat Ananthan, Wayne R French
  • Publication number: 20150137062
    Abstract: Selector devices suitable for memory arrays have low leakage currents at low voltages, reducing sneak current paths for non-selected devices, and high leakage currents at high voltages, reducing voltage drops during switching. The selector device may include a non-conductive tri-layer between two electrodes. The non-conductive tri-layer may include a low-bandgap dielectric layer between two higher-bandgap dielectric layers. The high-bandgap dielectric layers may be doped to form traps at energy levels higher than the write voltage of the memory device. With a thin low-bandgap layer and a large bandgap difference from the high-bandgap layers, the selector may operate as a quantum well, conductive when the electrode Fermi level matches the lowest energy level of the quantum well and insulating at lower voltages.
    Type: Application
    Filed: December 4, 2014
    Publication date: May 21, 2015
    Inventors: Venkat Ananthan, Prashant B Phatak
  • Publication number: 20150140772
    Abstract: Selector devices that can be suitable for memory device applications can have low leakage currents at low voltages to reduce sneak current paths for non selected devices, and high leakage currents at high voltages to minimize voltage drops during device switching. The selector device can include a first electrode, a tri-layer dielectric layer, and a second electrode. The tri-layer dielectric layer can include a low band gap dielectric layer disposed between two higher band gap dielectric layers. The high band gap dielectric layers can be doped with doping materials to form traps at energy levels higher than the operating voltage of the memory device.
    Type: Application
    Filed: December 3, 2014
    Publication date: May 21, 2015
    Inventors: Venkat Ananthan, Prashant B. Phatak
  • Patent number: 9029187
    Abstract: Selector devices that can be suitable for memory device applications can have low leakage currents at low voltages to reduce sneak current paths for non selected devices, and high leakage currents at high voltages to minimize voltage drops during device switching. The selector device can include a first electrode, a tri-layer dielectric layer, and a second electrode. The tri-layer dielectric layer can include a low band gap dielectric layer disposed between two higher band gap dielectric layers. The high band gap dielectric layers can be doped with doping materials to form traps at energy levels higher than the operating voltage of the memory device.
    Type: Grant
    Filed: December 3, 2014
    Date of Patent: May 12, 2015
    Assignee: Intermolecular, Inc.
    Inventors: Venkat Ananthan, Prashant B Phatak
  • Patent number: 8980653
    Abstract: The embodiments describe methods and apparatuses for combinatorial optimization of interlayer parameters for capacitor stacks. The capacitor stacks may include a substrate, an insulating layer disposed on the substrate, a ruthenium disposed electrode on the insulating layer, and an interlayer disposed on the ruthenium electrode, where the interlayer is configured to prevent etching of the electrode when growing a high-k dielectric using an ozone-based precursor. The parameters for forming the interlayer may include interlayer thickness, precursor chemistry, oxidant strength, precursor purge times, oxidant purge times, and other suitable parameters. Each of these parameters may be evaluated through deposition of the capacitor stacks through a combinatorial optimization process. Thus, a plurality of different parameters may be evaluated with a single substrate to ascertain associated properties of Ruthenium electrode etching in a combinatorial manner.
    Type: Grant
    Filed: September 19, 2012
    Date of Patent: March 17, 2015
    Assignee: Intermolecular, Inc.
    Inventor: Venkat Ananthan
  • Patent number: 8981335
    Abstract: Resistive random access memory (ReRAM) cells can include a ZnTe switching layer and TiN or Pt electrodes. The combination of the switching layer of ZnTe and the electrodes of TiN or Pt is designed to achieve desirable performance characteristics, such as low current leakage as well as low and consistent switching currents. High temperature anneal of the ZnTe switching layer can further improve the performance of the ReRAM cells. The switching layer may be deposited using various techniques, such as sputtering or atomic layer deposition (ALD).
    Type: Grant
    Filed: November 6, 2013
    Date of Patent: March 17, 2015
    Assignee: Intermolecular, Inc.
    Inventors: Venkat Ananthan, Prashant B. Phatak
  • Patent number: 8933429
    Abstract: Selector devices that can be suitable for memory device applications can have low leakage currents at low voltages to reduce sneak current paths for non selected devices, and high leakage currents at high voltages to minimize voltage drops during device switching. The selector device can include a first electrode, a tri-layer dielectric layer, and a second electrode. The tri-layer dielectric layer can include a low band gap dielectric layer disposed between two higher band gap dielectric layers. The high band gap dielectric layers can be doped with doping materials to form traps at energy levels higher than the operating voltage of the memory device.
    Type: Grant
    Filed: August 23, 2013
    Date of Patent: January 13, 2015
    Assignee: Intermolecular, Inc.
    Inventors: Venkat Ananthan, Prashant B Phatak
  • Publication number: 20150001676
    Abstract: MIMCAP devices are provided that can be suitable for memory device applications, such as current selector devices for cross point memory array. The MIMCAP devices can have lower thermal budget as compared to Schottky diodes and controllable lower barrier height and lower series resistance as compared to MIMCAP tunneling diodes. The MIMCAP diode can include a low defect dielectric layer, a high defect dielectric layer, sandwiched between two electrodes having different work function values.
    Type: Application
    Filed: September 19, 2014
    Publication date: January 1, 2015
    Inventors: Venkat Ananthan, Imran Hashim, Prashant B. Phatak
  • Patent number: 8871621
    Abstract: MIMCAP devices are provided that can be suitable for memory device applications, such as current selector devices for cross point memory array. The MIMCAP devices can have lower thermal budget as compared to Schottky diodes and controllable lower barrier height and lower series resistance as compared to MIMCAP tunneling diodes. The MIMCAP diode can include a low defect dielectric layer, a high defect dielectric layer, sandwiched between two electrodes having different work function values.
    Type: Grant
    Filed: December 20, 2012
    Date of Patent: October 28, 2014
    Assignee: Intermolecular, Inc.
    Inventors: Venkat Ananthan, Imran Hashim, Prashant B. Phatak
  • Publication number: 20140264239
    Abstract: Selector devices that can be suitable for memory device applications can have low leakage currents at low voltages to reduce sneak current paths for non selected devices, and high leakage currents at high voltages to minimize voltage drops during device switching. The selector device can include a first electrode, a tri-layer dielectric layer, and a second electrode. The tri-layer dielectric layer can include a low band gap dielectric layer disposed between two higher band gap dielectric layers. The high band gap dielectric layers can be doped with doping materials to form traps at energy levels higher than the operating voltage of the memory device.
    Type: Application
    Filed: August 23, 2013
    Publication date: September 18, 2014
    Applicant: Intermolecular Inc.
    Inventors: Venkat Ananthan, Prashant B. Phatak
  • Publication number: 20140264241
    Abstract: Resistive random access memory (ReRAM) cells can include a ZnTe switching layer and TiN or Pt electrodes. The combination of the switching layer of ZnTe and the electrodes of TiN or Pt is designed to achieve desirable performance characteristics, such as low current leakage as well as low and consistent switching currents. High temperature anneal of the ZnTe switching layer can further improve the performance of the ReRAM cells. The switching layer may be deposited using various techniques, such as sputtering or atomic layer deposition (ALD).
    Type: Application
    Filed: November 6, 2013
    Publication date: September 18, 2014
    Applicant: Intermolecular, Inc.
    Inventors: Venkat Ananthan, Prashant B. Phatak