Abstract: A method for simulating a tucked transistor device having a diffusion region defined in a semiconductor layer, a gate electrode adjacent a first side of the diffusion region, a floating gate electrode adjacent a second side of the diffusion region, and an isolation structure disposed beneath at least a portion of the floating gate electrode is provided. The method includes receiving a first netlist having an entry for the tucked transistor device in a computing apparatus. The entry defines parameters associated with the gate electrode and the diffusion region. A parasitic capacitance component is added to the entry representing a gate capacitance between the floating gate and the diffusion region in the computing apparatus.

Abstract: A tucked transistor device has a diffusion region defined in a semiconductor layer, a switching gate electrode adjacent a first side of the diffusion region, a floating gate electrode adjacent a second side of the diffusion region, and an isolation structure disposed beneath at least a portion of the floating gate electrode. A method includes receiving a netlist having an entry for the tucked transistor device in a computing apparatus, the entry defining parameters associated with the switching gate electrode and the diffusion region, receiving a device parameter file including at least a gate bounded junction capacitance parameter that includes a junction capacitance bounded by the switching gate electrode modified to include a contribution of the floating gate electrode to a gate bounded junction capacitance of the tucked transistor device. Operation of the tucked transistor device is simulated in the computing apparatus using a transistor device model and the netlist.

Abstract: A method for simulating a tucked transistor device having a diffusion region defined in a semiconductor layer, a gate electrode adjacent a first side of the diffusion region, a floating gate electrode adjacent a second side of the diffusion region, and an isolation structure disposed beneath at least a portion of the floating gate electrode is provided. The method includes receiving a first netlist having an entry for the tucked transistor device in a computing apparatus. The entry defines parameters associated with the gate electrode and the diffusion region. A parasitic capacitance component is added to the entry representing a gate capacitance between the floating gate and the diffusion region in the computing apparatus.