Patents by Inventor Venkata Aditya Addepalli

Venkata Aditya Addepalli has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240178227
    Abstract: Integrated circuit structures having uniformity among varying gate trench widths are described. For example, an integrated circuit structure includes a first fin, and a first gate trench over the first fin, the first gate trench having a first width. The integrated circuit structure also includes a second fin, and a second gate trench over the second fin, the second gate trench having a second width greater than the first width. The integrated circuit structure also includes a gate electrode layer having a first portion along a bottom and partially along sidewalls of the first trench, and the gate electrode layer having a second portion along a bottom and partially along sidewalls of the second trench, wherein the first portion extends along the sidewalls of the first trench to approximately the same extent as the second portion extends along the sidewalls of the second trench.
    Type: Application
    Filed: November 30, 2022
    Publication date: May 30, 2024
    Inventors: Venkata Aditya ADDEPALLI, Shyam Benegal KADALI
  • Publication number: 20230395697
    Abstract: A semiconductor structure includes a second device stacked over a first device. In an example, the first device includes (i) a first source region, (ii) a first drain region, (iii) a body including a semiconductor material extending laterally from the first source region to the first drain region, and (iv) a first gate structure at least in part wrapped around the body. The body can be, for instance, a nanoribbon, nanosheet, or nanowire. In an example, the second device comprises (i) a second source region, (ii) a second drain region, and (iii) a second gate structure at least in part laterally between the second source region and the second drain region. In an example, the second device lacks a continuous body extending laterally from the second source region to the second drain region.
    Type: Application
    Filed: June 3, 2022
    Publication date: December 7, 2023
    Applicant: Intel Corporation
    Inventors: Nicole K. Thomas, Munzarin F. Qayyum, Marko Radosavljevic, Cheng-Ying Huang, Willy Rachmady, Rohit Galatage, Jami A. Wiedemer, David Bennett, Dincer Unluer, Venkata Aditya Addepalli