Abstract: Systems and methods are disclosed for providing micro-idle memory power management. One embodiment of a method comprises receiving and storing an exit latency vote from each of a plurality of memory subsystems on a system on chip electrically coupled to a system memory. In response to a micro-idle memory state in which each of the memory subsystems are idle, a minimum exit latency value from the plurality of exit latency votes is determined. One of a plurality of system memory modes is selected which has a micro-idle sleep time that meets the minimum exit latency value while minimizing system memory power consumption. The selected system memory mode is initiated.

Abstract: A method for reducing power in a system is provided according to aspects of the present disclosure. The system includes a chip, and a volatile memory. The method includes entering a sleep state, and exiting the sleep state. Entering the sleep state includes placing the volatile memory in a self-refresh mode, wherein the volatile memory stores one or more binary images and the volatile memory is powered in the sleep state, and collapsing multiple power supply rails on the chip. Exiting the sleep state includes restoring power to the multiple power supply rails on the chip, taking the volatile memory out of the self-refresh mode, and running the one or more binary images on one or more sub-systems on the chip.

Abstract: Aspects of the disclosure are directed to DC power management. A sequencer may be configured to execute a first command, wherein the first command is associated with a unique group tag; compare the unique group tag to a master group tag; determine if an interrupt is detected; lock the master group tag to yield a locked master group tag; execute a second command, wherein the second command is associated with the locked master group tag; determine that an end of commands in the locked master group tag is reached and execute a sequence jump through command to put a processor back to a regular power state.

Abstract: Aspects of the disclosure are directed to DC power management. A sequencer may be configured to execute a first command, wherein the first command is associated with a unique group tag; compare the unique group tag to a master group tag; determine if an interrupt is detected; lock the master group tag to yield a locked master group tag; execute a second command, wherein the second command is associated with the locked master group tag; determine that an end of commands in the locked master group tag is reached and execute a sequence jump through command to put a processor back to a regular power state.

Abstract: A method for reducing power in a system is provided according to aspects of the present disclosure. The system includes a chip, and a volatile memory. The method includes entering a sleep state, and exiting the sleep state. Entering the sleep state includes placing the volatile memory in a self-refresh mode, wherein the volatile memory stores one or more binary images and the volatile memory is powered in the sleep state, and collapsing multiple power supply rails on the chip. Exiting the sleep state includes restoring power to the multiple power supply rails on the chip, taking the volatile memory out of the self-refresh mode, and running the one or more binary images on one or more sub-systems on the chip.

Abstract: A method and an apparatus for providing a power grid are provided. The apparatus includes a plurality of memory units comprising at least one SoC memory and at least one cache memory. The apparatus includes a first subsystem coupled to the at least one SoC memory associated with a first power domain. The apparatus further includes a second subsystem coupled to the at least one cache memory associated with a second power domain. The second subsystem may be a CPU subsystem. Because the first power domain sources power from a shared power source, the first power domain may operate at a voltage level that is higher than the operation of memory circuits requires. By moving the at least one cache memory from the first power domain to the second power domain, LDO efficiency loss for components in the first power domain may be reduced.

Abstract: A method and an apparatus for providing a power grid are provided. The apparatus includes a plurality of memory units comprising at least one SoC memory and at least one cache memory. The apparatus includes a first subsystem coupled to the at least one SoC memory associated with a first power domain. The apparatus further includes a second subsystem coupled to the at least one cache memory associated with a second power domain. The second subsystem may be a CPU subsystem. Because the first power domain sources power from a shared power source, the first power domain may operate at a voltage level that is higher than the operation of memory circuits requires. By moving the at least one cache memory from the first power domain to the second power domain, LDO efficiency loss for components in the first power domain may be reduced.