Abstract: A method of compacting a circuit layout includes determining a critical path of the circuit layout, the critical path having a length not less than a length of each other path of the circuit layout. The method further includes representing the critical path to include a plurality of vertices and a plurality of edges, each one of the vertices being coupled to another of the vertices by an edge, the plurality of vertices including a flexible vertex corresponding to a flexible element of the circuit layout, the plurality of edges including a first shear edge. The method further includes representing the flexible vertex to include a first jogging edge. The method further includes determining an optimal cutest of the graph of the critical path, the cutest including at least one of the group consisting of the first jogging edge and the first shear edge.

Abstract: The present layout compaction technique compacts circuit elements in two dimensions of a circuit layout with reduced computational requirements. A circuit layout representation is converted to a constraint graph representation in a reference direction. An orthogonal constraint graph is also constructed. A critical path subgraph is constructed based upon the reference and orthogonal constraint graphs, where one or more critical paths are chosen as the longest paths between the source and sink vertices of the reference constraint graph. Further, each vertex in the constraint graph is converted to an input vertex for each incoming shear edge and an output vertex for each outgoing shear edge. Jogging edges are created between each input and output vertices in the critical path subgraph. Weight values are assigned to each shear and jogging edge.

Abstract: A method for optimizing contact pin placement in an integrated circuit, wherein a netlist containing connectivity information, and placement information for a semiconductor circuit is read. Each net in the circuit is classified (510). Unblocked tracks are identified for each net in the circuit (512). All contact pins associated with nets having a power supply classification are placed according to a power supply location (513). The blockage for each remaining net is updated. Next, all contact pins for nets residing within a defined diffusion are placed (514) The blockage for each remaining net is updated. Next, all contact pins for nets residing in multiple defined diffusion areas are placed (515).

Abstract: A method for automatically synthesizing standard cell layouts(170) given a circuit netlist, a template describing the layout style and a set of process design rules (136) starts by numerating an ordered sequence of physical netlists from the logical netlist(138). Next, a netlist is selected from the ordered sequence of physical netlists (140). Components are placed according to the selected physical netlist (144). The components are routed to implement interconnections specified by the netlist (154). The components are compacted (156). A next netlist is selected from the ordered sequence of physical netlists. The steps of placing, routing and compacting the components are repeated. The layout with the smallest width is selected(166). Finally, ies, contacts and vias are added and notches filled (170) to improve yield and performance of the circuit.

Abstract: A method of interconnecting transistors and other devices in order to optimize area of a layout of a cell while honoring performance constraints (1502) and enhancing yield starts with a prerouting step (152) that routes adjacent transistors using diffusion wiring (1506), routes power and ground nets (1508), routes aligned gates (1510), routes all remaining aligned source/drain nets as well as any special nets (1512). Next, all of the remaining nets are routed using an area based router (1408). Nets are order based on time criticality or net topology (1602). A routing grid is assigned for all the layers to be used in routing (1604). An initial coarse routing is performed (1606). Wire groups are assigned to routing layers (1608). Routing is improved and vias are minimized (1610). A determination is then made whether the routing solution is acceptable (1612). If the routintg solution is not acceptable, the routing space is expanded and routing costs and via costs are modifyied to improve the routing solution.