Abstract: A method stores data that handles page faults in an appropriate memory device based on a standing memory policy. One or more processors receive user requested memory buffer attributes that describe memory buffer attributes needed for various processes. The processor(s) store the user requested memory buffer attributes in an operating system virtual memory representation that describes various types of memories used by the system, create a standing memory policy based on the user requested memory buffer attributes, and store data on an appropriate memory device based on the standing memory policy. The processor(s) receive a page fault, which is based on the data being called by a process but not being currently mapped by a memory management unit (MMU) into a virtual address space of the process. The processor(s) then retrieve and return the data stored on the appropriate memory device in order to address the page fault.

Abstract: A system and method for storing data that includes at least one memory device having a plurality of memory cells for storing data; and a memory control circuit that manages the read current and read pulse width applied to the memory cells, wherein the at least one memory device has a read current circuit configured to utilize adjustments to at least one of the read current or the read pulse width applied to the memory cells. In response to a request to read a group of the memory cells, the memory control circuit in an example, in response to determining that a comparative temperature value exceeds a first threshold, is configured to perform at least one of reducing the read current and/or increasing the read pulse width to be applied to the group of memory devices to be read.

Abstract: A system, method, and computer program product are provided herein to manage DRAM bank activation per cycle. A memory controller with embedded scheduling logic is employed to manage the system, method, and computer program product and to restrict the quantity of active banks in a given cycle, resulting in power savings with minimal performance loss, if any. The scheduling logic provides instructions to manage the state of associated DRAM banks. Each bank is either in an idle state or an active state, with the idle state consuming less power than the active state. The scheduling logic restricts the quantity of active banks in any cycle, with all other banks being in an idle state, which provides power savings to the associated system.

Abstract: A system and method for storing data that includes at least one memory device having a plurality of memory cells for storing data; and a memory control circuit that manages the read current and read pulse width applied to the memory cells, wherein the at least one memory device has a read current circuit configured to utilize adjustments to at least one of the read current or the read pulse width applied to the memory cells. In response to a request to read a group of the memory cells, the memory control circuit in an example, in response to determining that a comparative temperature value exceeds a first threshold, is configured to perform at least one of reducing the read current and/or increasing the read pulse width to be applied to the group of memory devices to be read.

Abstract: A computer-implemented method, according to one embodiment, includes: determining a current temperature associated with an intended storage location in memory for data in a write request, determining a percentage of first logical states included in a binary representation of the data in the received write request, selecting a write management operation in response to determining that the current temperature associated with the intended storage location is outside a predetermined range, and sending one or more instructions to perform the write management operation. Moreover, the write management operation corresponds to the determined percentage of first logical states included in the binary representation. Other systems, methods, and computer program products are described in additional embodiments.

Abstract: A method handles cache misses using a Scope Resolution Tag Buffer (SRTB). A cache controller assigns each data block in L2 cache with an n-bit value, where the n-bit value describes a quantity of occurrences in which the data block has been accessed, and where the cache controller increments the n-bit value in one or more data blocks in the first level memory cache each time the one or more data blocks are accessed. The cache controller evicts a particular data block from the L2 cache, and stores a particular data block address where the particular data block is now stored in a Scope Resolution Tag Buffer (SRTB). The information in the SRTB is used to locate which cache or memory contains the particular data block in the event of a subsequent cache miss in the L2 cache.

Abstract: Predicting physical memory attributes by compiler analysis of code blocks includes receiving source code including at least one code block, and identifying a buffer associated with the at least one code block. Buffer access characteristics associated with the buffer are determined from the at least one code block. The buffer access characteristics are mapped to physical memory attributes associated with one or more physical memories of a computing system. Executable program code including a system call associated with memory allocation is generated based upon the physical memory attribute values.

Abstract: Predicting physical memory attributes by compiler analysis of code blocks includes receiving source code including at least one code block, and identifying a buffer associated with the at least one code block. Buffer access characteristics associated with the buffer are determined from the at least one code block. The buffer access characteristics are mapped to physical memory attributes associated with one or more physical memories of a computing system. Executable program code including a system call associated with memory allocation is generated based upon the physical memory attribute values.

Abstract: A method handles cache misses using a Scope Resolution Tag Buffer (SRTB). A cache controller assigns each data block in L2 cache with an n-bit value, where the n-bit value describes a quantity of occurrences in which the data block has been accessed, and where the cache controller increments the n-bit value in one or more data blocks in the first level memory cache each time the one or more data blocks are accessed. The cache controller evicts a particular data block from the L2 cache, and stores a particular data block address where the particular data block is now stored in a Scope Resolution Tag Buffer (SRTB). The information in the SRTB is used to locate which cache or memory contains the particular data block in the event of a subsequent cache miss in the L2 cache.

Abstract: A method stores data that handles page faults in an appropriate memory device based on a standing memory policy. One or more processors receive user requested memory buffer attributes that describe memory buffer attributes needed for various processes. The processor(s) store the user requested memory buffer attributes in an operating system virtual memory representation that describes various types of memories used by the system, create a standing memory policy based on the user requested memory buffer attributes, and store data on an appropriate memory device based on the standing memory policy. The processor(s) receive a page fault, which is based on the data being called by a process but not being currently mapped by a memory management unit (MMU) into a virtual address space of the process. The processor(s) then retrieve and return the data stored on the appropriate memory device in order to address the page fault.

Abstract: A system, method, and computer program product are provided herein to manage DRAM bank activation per cycle. A memory controller with embedded scheduling logic is employed to manage the system, method, and computer program product and to restrict the quantity of active banks in a given cycle, resulting in power savings with minimal performance loss, if any. The scheduling logic provides instructions to manage the state of associated DRAM banks. Each bank is either in an idle state or an active state, with the idle state consuming less power than the active state. The scheduling logic restricts the quantity of active banks in any cycle, with all other banks being in an idle state, which provides power savings to the associated system.

Abstract: A system, method, and computer program product are provided herein to manage DRAM bank activation per cycle. A memory controller with embedded scheduling logic is employed to manage the system, method, and computer program product and to restrict the quantity of active banks in a given cycle, resulting in power savings with minimal performance loss, if any. The scheduling logic provides instructions to manage the state of associated DRAM banks. Each bank is either in an idle state or an active state, with the idle state consuming less power than the active state. The scheduling logic restricts the quantity of active banks in any cycle, with all other banks being in an idle state, which provides power savings to the associated system.

Abstract: A computer-implemented method, according to one embodiment, includes: determining a current temperature associated with an intended storage location in memory for data in a write request, determining a percentage of first logical states included in a binary representation of the data in the received write request, selecting a write management operation in response to determining that the current temperature associated with the intended storage location is outside a predetermined range, and sending one or more instructions to perform the write management operation. Moreover, the write management operation corresponds to the determined percentage of first logical states included in the binary representation. Other systems, methods, and computer program products are described in additional embodiments.

Abstract: Scheduling memory operations using bank groups including receiving, by a sequencing engine in a memory controller, a set of operations targeting locations in a memory device, wherein the memory device comprises a plurality of bank groups; determining, by the sequencing engine, a targeted bank group of each of the set of operations; selecting, by the sequencing engine, one of the set of operations based on the targeted bank group of each of the set of operations and a bank group of a previously sent operation; and sending, by the sequencing engine, the selected one of the set of operations to the memory device.

Abstract: A computer-implemented method, according to one embodiment, includes: receiving a write request, determining an intended storage location in memory for data in the received write request, determining a current temperature associated with the intended storage location, determining a percentage of first logical states included in a binary representation of the data in the received write request, selecting a write management operation in response to determining that the current temperature associated with the intended storage location is outside a predetermined range, and sending one or more instructions to perform the write management operation. Moreover, the write management operation corresponds to the determined percentage of first logical states included in the binary representation. Other systems, methods, and computer program products are described in additional embodiments.

Abstract: A system, method, and computer program product are provided herein to manage DRAM bank activation per cycle. A memory controller with embedded scheduling logic is employed to manage the system, method, and computer program product and to restrict the quantity of active banks in a given cycle, resulting in power savings with minimal performance loss, if any. The scheduling logic provides instructions to manage the state of associated DRAM banks. Each bank is either in an idle state or an active state, with the idle state consuming less power than the active state. The scheduling logic restricts the quantity of active banks in any cycle, with all other banks being in an idle state, which provides power savings to the associated system.

Abstract: Scheduling memory operations using bank groups including receiving, by a sequencing engine in a memory controller, a set of operations targeting locations in a memory device, wherein the memory device comprises a plurality of bank groups; determining, by the sequencing engine, a targeted bank group of each of the set of operations; selecting, by the sequencing engine, one of the set of operations based on the targeted bank group of each of the set of operations and a bank group of a previously sent operation; and sending, by the sequencing engine, the selected one of the set of operations to the memory device.

Abstract: An aspect includes reading a plurality of sensor values from a plurality of sensors located on a plurality of memory dies in the HMC. It is determined that one of the plurality of sensor values from a sensor located on one of the plurality of memory dies has exceeded a threshold value. Based on the determining and on the one of the plurality of sensor values, calculating a refresh rate for the memory locations on the one of the plurality of memory dies. The vault controller is reconfigured to apply the calculated die refresh rate to the memory locations in the vault that are located on the one of the plurality of memory dies. The calculated die refresh rate is different than an other refresh rate being applied to memory locations in the vault that are located on an other one of the plurality of memory dies.