Abstract: A processor of a host can define a plurality of relationships in a virtual environment. The processor of the host can also provide the plurality of inputs describing look preferences to an AI accelerator. The AI accelerator can receive the inputs. The AI accelerator can also generate a plurality of looks based on the plurality of relationships and the plurality of inputs.

Abstract: Methods, systems, and devices for a read operation using compressed memory are described. An apparatus may include a host system coupled with a non-volatile memory device and a volatile memory device. The host system may store, in the volatile memory device, a compressed copy of data stored in the non-volatile memory device, for example, based on a score assigned to the data. The host system may identify that the compressed copy of the data is stored in the volatile memory device and may transmit a read command to the volatile memory device that includes a logical address associated with a logical block address of the data stored in the non-volatile memory device. The host system may receive the compressed copy of the data from the volatile memory device in response to the read command and may decompress the data.

Abstract: A controller can be directly coupled to a storage device and a memory device but not a host. The controller can monitor a plurality of regions of the memory device to determine whether the plurality of regions meet a criterion for fullness and responsive to determining that the plurality of regions meet the criterion, read data from the plurality of regions. The controller can, responsive to reading the data from the plurality of regions, store the data in the storage device and delete the data from the plurality of regions. The controller can further, responsive to storing the data, report to a host that the data has been moved from the memory device to the storage device. The controller can be implemented independent from the host.

Abstract: Methods, systems, and devices for dynamic logical page sizes for memory devices are described. A memory device may use an initial set of logical pages each having a same size and one or more logical-to-physical (L2P) tables to map logical addresses of the logical pages to the physical addresses of corresponding physical pages. As commands are received from a host device, the memory device may dynamically split a logical page to introduce smaller logic pages if the host device accesses data in chunk sizes smaller than the size of the logical page that is split. The memory device may maintain one or more additional L2P tables for each smaller logical page size that is introduced, along with one or more pointer tables to map between L2P tables and entries for larger logical page sizes and L2P tables and entries associated with smaller logical page sizes.

Abstract: Methods, systems, and devices for write buffer extensions for storage interface controllers are described. Apparatuses and methods are presented in which a buffer may be used to temporarily store data from an application if the memory device is in an INACTIVE power mode. This may allow the memory device to remain asleep. The buffer may be positioned on the host device so that the power mode of the memory device may not affect it. That way, data may be stored in the buffer without waking up the memory device. If the memory device is in an ACTIVE power mode, the data that has been temporarily stored in the buffer may be sent to the memory device for storage. During read operations, if the requested data is stored in the buffer, it may be used instead of data in the memory device.

Abstract: Methods, systems, and devices for session-based memory operation are described. A memory system may determine that a logical address targeted by a read command is associated with a session table. The memory system may write the session table to a cache based on the logical address being associated with the session table. After writing the session table to the cache, the memory system may use the session table to determine one or more logical-to-physical (L2P) tables and write the one or more L2P tables to the cache. The memory system may use the L2L tables to perform address translation for logical addresses.

Abstract: Methods, systems, and devices for rate adjustments for a memory interface are described. A host system may communicate with a memory system via an interface according to multiple data transfer rates. For example, the host system may configure the interface to operate according to a first rate. The host system may switch the interface from the first rate to a second rate in response to one or more commands from the host system satisfying one or more parameters such as a threshold quantity of data associated with a command, a threshold quantity of issued commands associated with at least the threshold quantity of data, a threshold quantity of issued and unexecuted commands, or any combination thereof. Based on the switching, the host system may communicate with the memory system via the interface in accordance with the second rate.

Abstract: Methods, systems, and devices for dynamic logical page sizes for memory devices are described. A memory device may use an initial set of logical pages each having a same size and one or more logical-to-physical (L2P) tables to map logical addresses of the logical pages to the physical addresses of corresponding physical pages. As commands are received from a host device, the memory device may dynamically split a logical page to introduce smaller logic pages if the host device accesses data in chunk sizes smaller than the size of the logical page that is split. The memory device may maintain one or more additional L2P tables for each smaller logical page size that is introduced, along with one or more pointer tables to map between L2P tables and entries for larger logical page sizes and L2P tables and entries associated with smaller logical page sizes.

Abstract: Methods, systems, and devices for a read operation using compressed memory are described. An apparatus may include a host system coupled with a non-volatile memory device and a volatile memory device. The host system may store, in the volatile memory device, a compressed copy of data stored in the non-volatile memory device, for example, based on a score assigned to the data. The host system may identify that the compressed copy of the data is stored in the volatile memory device and may transmit a read command to the volatile memory device that includes a logical address associated with a logical block address of the data stored in the non-volatile memory device. The host system may receive the compressed copy of the data from the volatile memory device in response to the read command and may decompress the data.

Abstract: Methods, systems, and devices for dynamic logical page sizes for memory devices are described. A memory device may use an initial set of logical pages each having a same size and one or more logical-to-physical (L2P) tables to map logical addresses of the logical pages to the physical addresses of corresponding physical pages. As commands are received from a host device, the memory device may dynamically split a logical page to introduce smaller logic pages if the host device accesses data in chunk sizes smaller than the size of the logical page that is split. The memory device may maintain one or more additional L2P tables for each smaller logical page size that is introduced, along with one or more pointer tables to map between L2P tables and entries for larger logical page sizes and L2P tables and entries associated with smaller logical page sizes.

Abstract: Methods, systems, and devices for session-based memory operation are described. A memory system may determine that a logical address targeted by a read command is associated with a session table. The memory system may write the session table to a cache based on the logical address being associated with the session table. After writing the session table to the cache, the memory system may use the session table to determine one or more logical-to-physical (L2P) tables and write the one or more L2P tables to the cache. The memory system may use the L2L tables to perform address translation for logical addresses.

Abstract: The various aspects provide methods, systems, and devices for coordinating the operating states of multiple SOCs within a computing device. Such coordination may be implemented through communication of information by the SOCs that represent advance notice of impending interactions between each other. The communicated information may be used by a recipient SOC for setting its operating state in advance of the potential impending interaction with another SOC. Accordingly, this technical improvement enables individual SOCs to preemptively influence the operating states of the other SOCs. For example, in the context of power management, the various aspects may coordinate the power states of multiple SOCs, thereby effectively implementing a monolithic power management state machine that improves overall power consumption of the computing device.

Abstract: The various aspects provide methods, systems, and devices for coordinating the operating states of multiple SOCs within a computing device. Such coordination may be implemented through communication of information by the SOCs that represent advance notice of impending interactions between each other. The communicated information may be used by a recipient SOC for setting its operating state in advance of the potential impending interaction with another SOC. Accordingly, this technical improvement enables individual SOCs to preemptively influence the operating states of the other SOCs. For example, in the context of power management, the various aspects may coordinate the power states of multiple SOCs, thereby effectively implementing a monolithic power management state machine that improves overall power consumption of the computing device.