Patents by Inventor Venkata Kottapalli

Venkata Kottapalli has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11767884
    Abstract: A bearing assembly is disclosed herein. The bearing assembly includes an outer bearing ring including at least one first connection element. The assembly also includes a cap defining an axial portion and at least one radial portion defining a cavity configured to receive the outer bearing ring. The cap includes at least one second connection element configured to mate with the at least one first connection element. The cap is formed from an electrically insulating material to prevent EDM.
    Type: Grant
    Filed: October 14, 2021
    Date of Patent: September 26, 2023
    Assignee: Schaeffler Technologies AG & Co. KG
    Inventors: Guihui Zhong, Venkata Kottapalli, Michael Heaton, John Tate, Charles Schwab
  • Publication number: 20230122158
    Abstract: A bearing assembly is disclosed herein. The bearing assembly includes an outer bearing ring including at least one first connection element. The assembly also includes a cap defining an axial portion and at least one radial portion defining a cavity configured to receive the outer bearing ring. The cap includes at least one second connection element configured to mate with the at least one first connection element. The cap is formed from an electrically insulating material to prevent EDM.
    Type: Application
    Filed: October 14, 2021
    Publication date: April 20, 2023
    Applicant: Schaeffler Technologies AG & CO. KG
    Inventors: Guihui Zhong, Venkata Kottapalli, Michael Heaton, John Tate, Charles Schwab
  • Patent number: 11473628
    Abstract: A bearing includes an integrated electrical shunt. The shunt includes electrically conductive fibers sandwiched between two washers, at least one of which is electrically conductive. The fibers are fastened to the electrically conductive washer by electrically conductive epoxy. An outer shield protects the fibers. The outer shield is held to the washers by a drawn cup. The washers, the drawn cup, and the outer shield all have oil drain holes to allow lubricant to flow to the rollers.
    Type: Grant
    Filed: July 21, 2021
    Date of Patent: October 18, 2022
    Assignee: Schaeffler Technologies AG & Co. KG
    Inventors: Marion Jack Ince, Venkata Kottapalli, Guihui Zhong
  • Patent number: 11391324
    Abstract: An improved arrangement and method for preventing bearing ring creep is disclosed herein. The method includes providing a bearing ring including a radial surface having at least one spiral groove. The at least one groove has edge breaks connecting lateral sides to the radial surface of the bearing ring. The method includes arranging the bearing ring inside of a housing or around a shaft such that the radial surface of the bearing ring is arranged adjacent to an inner surface of the housing or an outer surface of the shaft. The edge breaks of the bearing ring frictionally engage with the shaft or the housing to prevent creep of the bearing ring.
    Type: Grant
    Filed: April 7, 2021
    Date of Patent: July 19, 2022
    Assignee: SCHAEFFLER TECHNOLOGIES AG & CO. KG
    Inventors: Guihui Zhong, Marion Jack Ince, Venkata Kottapalli, Arjun Kailassh Magalingam Adithyan
  • Publication number: 20220018399
    Abstract: A bearing includes an integrated electrical shunt. The shunt includes electrically conductive fibers sandwiched between two washers, at least one of which is electrically conductive. The fibers are fastened to the electrically conductive washer by electrically conductive epoxy. An outer shield protects the fibers. The outer shield is held to the washers by a drawn cup. The washers, the drawn cup, and the outer shield all have oil drain holes to allow lubricant to flow to the rollers.
    Type: Application
    Filed: July 21, 2021
    Publication date: January 20, 2022
    Applicant: Schaeffler Technologies AG & Co. KG
    Inventors: Marion Jack Ince, Venkata Kottapalli, Guihui Zhong
  • Patent number: 11111962
    Abstract: A bearing includes an integrated electrical shunt. The shunt includes electrically conductive fibers sandwiched between two washers, at least one of which is electrically conductive. The fibers are fastened to the electrically conductive washer by electrically conductive epoxy. An outer shield protects the fibers. The outer shield is held to the washers by a drawn cup. The washers, the drawn cup, and the outer shield all have oil drain holes to allow lubricant to flow to the rollers.
    Type: Grant
    Filed: July 16, 2020
    Date of Patent: September 7, 2021
    Assignee: Schaeffler Technologies AG & Co. KG
    Inventors: Marion Jack Ince, Venkata Kottapalli, Guihui Zhong
  • Patent number: 10907687
    Abstract: An outer ring for a deep groove ball bearing assembly is disclosed. The outer ring includes a radially inner surface defining a raceway, and a radially outer surface defining a single groove extending between axial ends of the outer ring. The single groove contacts at least one axial end face of the outer ring.
    Type: Grant
    Filed: March 9, 2020
    Date of Patent: February 2, 2021
    Assignee: Schaeffler Technologies AG & Co. KG
    Inventors: Guihui Zhong, Marion Jack Ince, Venkata Kottapalli
  • Patent number: 10883541
    Abstract: A bearing includes an inner ring having an outer surface defining a first pocket therein. The surface of the first pocket can be provided with a first conductive coating. The bearing includes an outer ring concentric with and radially outward from the inner ring. The outer ring has an inner surface defining a second pocket therein, and a surface of the second pocket can be provided with a second conductive coating. A plurality of rolling elements are disposed between the inner ring and the outer ring. An electrically-conductive shunt ring assembly couples the inner ring to the outer ring and is configured to inhibit electrical current passing between the inner ring and outer ring from passing through the rolling elements. The shunt ring assembly is sized and configured to enable lubricant to flow freely through the bearing. In some embodiments, the shunt ring is a conductive snap ring.
    Type: Grant
    Filed: February 19, 2019
    Date of Patent: January 5, 2021
    Assignee: SCHAEFFLER TECHNOLOGIES AG & CO. KG
    Inventors: Venkata Kottapalli, Hareshkumar Dalsaniya, Daniel Wise
  • Publication number: 20200263734
    Abstract: A bearing includes an inner ring having an outer surface defining a first pocket therein. The surface of the first pocket can be provided with a first conductive coating. The bearing includes an outer ring concentric with and radially outward from the inner ring. The outer ring has an inner surface defining a second pocket therein, and a surface of the second pocket can be provided with a second conductive coating. A plurality of rolling elements are disposed between the inner ring and the outer ring. An electrically-conductive shunt ring assembly couples the inner ring to the outer ring and is configured to inhibit electrical current passing between the inner ring and outer ring from passing through the rolling elements. The shunt ring assembly is sized and configured to enable lubricant to flow freely through the bearing. In some embodiments, the shunt ring is a conductive snap ring.
    Type: Application
    Filed: February 19, 2019
    Publication date: August 20, 2020
    Applicant: SCHAEFFLER TECHNOLOGIES AG & CO. KG
    Inventors: Venkata KOTTAPALLI, Hareshkumar DALSANIYA, Daniel WISE
  • Publication number: 20200208682
    Abstract: An outer ring for a deep groove ball bearing assembly is disclosed. The outer ring includes a radially inner surface defining a raceway, and a radially outer surface defining a single groove extending between axial ends of the outer ring. The single groove contacts at least one axial end face of the outer ring.
    Type: Application
    Filed: March 9, 2020
    Publication date: July 2, 2020
    Applicant: Schaeffler Technologies AG & Co. KG
    Inventors: Guihui Zhong, Marion Jack Ince, Venkata Kottapalli
  • Patent number: 10612595
    Abstract: A deep groove ball bearing assembly is disclosed. The assembly includes an inner bearing ring defining an inner race, an outer bearing ring defining an outer race, and a plurality of rolling elements supported on the inner race and the outer race. A shaft is supported on a radially inner surface of the inner bearing ring, and a housing is supported on a radially outer surface of the outer bearing ring. The assembly includes a contact surface on at least one of: the inner bearing ring, the outer bearing ring, the shaft, or the housing. The contact surface includes at least one lubrication groove.
    Type: Grant
    Filed: August 13, 2018
    Date of Patent: April 7, 2020
    Assignee: SCHAEFFLER TECHNOLOGIES AG & CO. KG
    Inventors: Guihui Zhong, Marion Jack Ince, Venkata Kottapalli
  • Publication number: 20200049200
    Abstract: A deep groove ball bearing assembly is disclosed. The assembly includes an inner bearing ring defining an inner race, an outer bearing ring defining an outer race, and a plurality of rolling elements supported on the inner race and the outer race. A shaft is supported on a radially inner surface of the inner bearing ring, and a housing is supported on a radially outer surface of the outer bearing ring. The assembly includes a contact surface on at least one of: the inner bearing ring, the outer bearing ring, the shaft, or the housing. The contact surface includes at least one lubrication groove.
    Type: Application
    Filed: August 13, 2018
    Publication date: February 13, 2020
    Applicant: Schaeffler Technologies AG & Co. KG
    Inventors: Guihui Zhong, Marion Jack Ince, Venkata Kottapalli
  • Patent number: 9911470
    Abstract: A memory circuit that presents input data at a data output promptly on receiving a clock pulse includes upstream and downstream memory logic and selection logic. The upstream memory logic is configured to latch the input data on receiving the clock pulse. The downstream memory logic is configured to store the latched input data. The selection logic is configured to expose a logic level dependent on whether the upstream memory logic has latched the input data, the exposed logic level derived from the input data before the input data is latched, and from the latched input data after the input data is latched.
    Type: Grant
    Filed: April 13, 2012
    Date of Patent: March 6, 2018
    Assignee: NVIDIA CORPORATION
    Inventors: Venkata Kottapalli, Scott Pitkethly, Christian Klingner, Matthew Gerlach
  • Patent number: 9885753
    Abstract: Efficient scan system presented can comprise: an array including a plurality of array non scannable components and a plurality of array quasi-scannable components wherein each column of the array includes at least one of the plurality of array quasi-scannable components; and an input interface configured to receive and selectively forward data and scan information to at least a portion of the array. At least a portion of the plurality of array quasi-scannable components can form a diagonal pattern in the array. The input interface can include: an input interface selection component wherein an output of the input interface selection component is communicatively coupled to an input of the input interface quasi-scannable component associated with one row and an input of the input interface selection component is communicatively coupled to an output of one of the plurality of array quasi-scannable components associated with another row.
    Type: Grant
    Filed: October 9, 2013
    Date of Patent: February 6, 2018
    Assignee: NVIDIA CORPORATION
    Inventors: Amit Sanghani, Farideh Golshan, Venkata Kottapalli, Milind Sonawane, Ketan Kulkarni
  • Publication number: 20150100840
    Abstract: Efficient scan system presented can comprise: an array including a plurality of array non scannable components and a plurality of array quasi-scannable components wherein each column of the array includes at least one of the plurality of array quasi-scannable components; and an input interface configured to receive and selectively forward data and scan information to at least a portion of the array. At least a portion of the plurality of array quasi-scannable components can form a diagonal pattern in the array. The input interface can include: an input interface selection component wherein an output of the input interface selection component is communicatively coupled to an input of the input interface quasi-scannable component associated with one row and an input of the input interface selection component is communicatively coupled to an output of one of the plurality of array quasi-scannable components associated with another row.
    Type: Application
    Filed: October 9, 2013
    Publication date: April 9, 2015
    Applicant: Nvidia Corporation
    Inventors: Amit SANGHANI, Farideh GOLSHAN, Venkata KOTTAPALLI, Milind SONAWANE, Ketan KULKARNI
  • Patent number: 8848458
    Abstract: A memory circuit in which a level of a first data input appears promptly at an output in response to a clock pulse received. The circuit includes a flip-flop triggered by the clock pulse and configured to receive the first data input and drive a second data input. The circuit also includes a first control input driven by the clock pulse, a second control input driven by the flip-flop and selection logic configured to receive the first and second data inputs and the first and second control inputs. The selection logic is configured to drive the output of the memory circuit to the level of the first data input or of the second data input depending on the first and second control inputs.
    Type: Grant
    Filed: December 15, 2011
    Date of Patent: September 30, 2014
    Assignee: Nvidia Corporation
    Inventors: Venkata Kottapalli, Scott Pitkethly, Christian Klingner, Matthew Gerlach
  • Patent number: 8803584
    Abstract: A level shifter circuit is disclosed that gates at least one of a plurality of input terminals of a level shifter to at least one of a plurality of supply voltages that are associated with respective supply voltage domains when the at least one of the plurality of supply voltages is powered down. The level shifter is therefore insensitive to noise on the input terminals and also reduces leakage current associated with noise induced crowbar currents.
    Type: Grant
    Filed: May 17, 2005
    Date of Patent: August 12, 2014
    Inventor: Venkata Kottapalli
  • Publication number: 20130155781
    Abstract: A memory circuit in which a level of a first data input appears promptly at an output in response to a clock pulse received. The circuit includes a flip-flop triggered by the clock pulse and configured to receive the first data input and drive a second data input. The circuit also includes a first control input driven by the clock pulse, a second control input driven by the flip-flop and selection logic configured to receive the first and second data inputs and the first and second control inputs. The selection logic is configured to drive the output of the memory circuit to the level of the first data input or of the second data input depending on the first and second control inputs.
    Type: Application
    Filed: December 15, 2011
    Publication date: June 20, 2013
    Applicant: NVIDIA CORPORATION
    Inventors: Venkata Kottapalli, Scott Pitkethly, Christian Klingner, Matthew Gerlach
  • Publication number: 20130155783
    Abstract: A memory circuit that presents input data at a data output promptly on receiving a clock pulse includes upstream and downstream memory logic and selection logic. The upstream memory logic is configured to latch the input data on receiving the clock pulse. The downstream memory logic is configured to store the latched input data. The selection logic is configured to expose a logic level dependent on whether the upstream memory logic has latched the input data, the exposed logic level derived from the input data before the input data is latched, and from the latched input data after the input data is latched.
    Type: Application
    Filed: April 13, 2012
    Publication date: June 20, 2013
    Applicant: NVIDIA CORPORATION
    Inventors: Venkata Kottapalli, Scott Pitkethly, Christian Klingner, Matthew Gerlach
  • Patent number: 7663408
    Abstract: A dynamic circuit latch, having the functionality of a domino circuit and a transparent latch, without the delay associated with the inclusion of a separate series latch element. Embodiments include a fast scannable footed Domino dyanmic latch. Also described is a fast scannable delay reset Domino dynamic latch. A fast scannable compound Domino dynamic latch is also described.
    Type: Grant
    Filed: June 30, 2005
    Date of Patent: February 16, 2010
    Inventors: Robert Paul Masleid, Jose Sousa, Venkata Kottapalli