Patents by Inventor Venkata Naga Jyothi Madhavapeddy

Venkata Naga Jyothi Madhavapeddy has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Re-adaption of equalizer parameter to center a sample point in a baud-rate clock and data recovery receiver
    Patent number: 8102910
    Abstract: An apparatus generally having a first circuit and a second circuit. The first circuit may be configured to (i) generate an equalizer parameter in response to an input signal, the equalizer parameter causing a cancellation of post-cursor inter-symbol interference from a plurality of symbols in the input signal and (ii) generate an output signal in response to both the input signal and the equalizer parameter. The second circuit may be configured to (i) generate a target parameter signal in response to the input signal, the target parameter signal representing a mean value of a plurality of sample points of the symbols and (ii) generate a control signal in response to the target parameter signal, the control signal causing a reduction of the equalizer parameter, the reduction causing a decrease in the cancellation of the post-cursor inter-symbol interference from the symbols, wherein the apparatus does not cancel pre-cursor inter-symbol interference.
    Type: Grant
    Filed: September 29, 2008
    Date of Patent: January 24, 2012
    Assignee: LSI Corporation
    Inventors: Freeman Y. Zhong, Amaresh V. Malipatil, Hollis H. Poche, Jr., Yikui Dong, Venkata Naga Jyothi Madhavapeddy