Abstract: Structures that include a peaking inductor and a T-coil, and methods associated with forming such structures. A back-end-of-line interconnect structure includes a first metallization level, a second metallization level, and a third metallization level arranged between the first metallization level and the second metallization level. The T-coil includes a first inductor with a first coil arranged in the first metallization level and a second inductor with a second coil arranged in the second metallization level. A peaking inductor includes a coil arranged in the third metallization level. The first coil of the first inductor, the second coil of the second inductor, and the coil of the peaking inductor are stacked in the back-end-of-line interconnect structure with an overlapping arrangement.

Abstract: Structures for a transistor including regions for landing gate contacts and methods of forming a structure for a transistor that includes regions for landing gate contacts. The structure includes a field-effect transistor having a source region, a gate region, a gate with a sidewall, and a gate extension with a section adjoined to the sidewall. The structure further includes a dielectric layer over the field-effect transistor, and a gate contact positioned in the dielectric layer to land on at least the section of the gate extension.

Abstract: Embodiments of the disclosure provide an integrated circuit (IC) structure, including a device layer including a device on a substrate. A local interconnect layer is over the device layer, and includes a first dielectric material over the substrate. The first dielectric material has a first effective dielectric constant. A second dielectric material is over the device and adjacent the first dielectric material. The second dielectric material has a second effective dielectric constant less than the first effective dielectric constant.

Abstract: Structures for a semiconductor device including airgap isolation and methods of forming a semiconductor device structure that includes airgap isolation. The structure includes a trench isolation region, an active region of semiconductor material surrounded by the trench isolation region, and a field-effect transistor including a gate within the active region. The structure further includes a dielectric layer over the field-effect transistor, a first gate contact coupled to the gate, and a second gate contact coupled to the gate. The first and second gate contacts are positioned in the dielectric layer over the active region, and the second gate contact is spaced along a longitudinal axis of the gate from the first gate contact. The structure further includes an airgap including a portion positioned in the dielectric layer over the gate between the first and second gate contacts.

Abstract: Structures for a semiconductor device including airgap isolation and methods of forming a semiconductor device structure that includes airgap isolation. The structure includes a trench isolation region, an active region of semiconductor material surrounded by the trench isolation region, and a field-effect transistor including a gate within the active region. The structure further includes a dielectric layer over the field-effect transistor, a first gate contact coupled to the gate, and a second gate contact coupled to the gate. The first and second gate contacts are positioned in the dielectric layer over the active region, and the second gate contact is spaced along a longitudinal axis of the gate from the first gate contact. The structure further includes an airgap including a portion positioned in the dielectric layer over the gate between the first and second gate contacts.

Abstract: The disclosure provides an integrated circuit (IC) structure with a body contact to a well with multiple diode junctions. A first doped well is in a substrate. A transistor is on the first doped well. A trench isolation (TI) is adjacent a portion of the first doped well. A second doped well within the substrate has a bottom surface beneath a bottom surface of the first doped well. A sidewall of the TI horizontally abuts the second doped well. A first diode junction is between the second doped well and the first doped well. A second diode junction is between the second doped well and the substrate. A body contact is on the second doped well.

Abstract: Embodiments of the disclosure provide an integrated circuit (IC) structure, including a device layer including a device on a substrate. A local interconnect layer is over the device layer, and includes a first dielectric material over the substrate. The first dielectric material has a first effective dielectric constant. A second dielectric material is over the device and adjacent the first dielectric material. The second dielectric material has a second effective dielectric constant less than the first effective dielectric constant.

Abstract: Embodiments of the disclosure provide an integrated circuit (IC) structure with a high impedance semiconductor material between a substrate and transistor. The IC structure may include: a substrate, a high impedance semiconductor material on a portion of the substrate, and a transistor on a top surface of the high impedance semiconductor material. The transistor includes a semiconductor channel region horizontally between a first source/drain (S/D) region and a second S/D region. The high impedance semiconductor material is vertically between the transistor and the substrate; a first insulator region is on the substrate and horizontally adjacent the first S/D region; and a first doped well is on the substrate and horizontally adjacent the first insulator region. The first insulator region is horizontally between the first doped well and the transistor.

Abstract: The disclosure provides an integrated circuit (IC) structure with a body contact to a well with multiple diode junctions. A first doped well is in a substrate. A transistor is on the first doped well. A trench isolation (TI) is adjacent a portion of the first doped well. A second doped well within the substrate has a bottom surface beneath a bottom surface of the first doped well. A sidewall of the TI horizontally abuts the second doped well. A first diode junction is between the second doped well and the first doped well. A second diode junction is between the second doped well and the substrate. A body contact is on the second doped well.

Abstract: Embodiments of the disclosure provide an integrated circuit (IC) structure with a high impedance semiconductor material between a substrate and transistor. The IC structure may include: a substrate, a high impedance semiconductor material on a portion of the substrate, and a transistor on a top surface of the high impedance semiconductor material. The transistor includes a semiconductor channel region horizontally between a first source/drain (S/D) region and a second S/D region. The high impedance semiconductor material is vertically between the transistor and the substrate; a first insulator region is on the substrate and horizontally adjacent the first S/D region; and a first doped well is on the substrate and horizontally adjacent the first insulator region. The first insulator region is horizontally between the first doped well and the transistor.

Abstract: Structures that include a peaking inductor and a T-coil, and methods associated with forming such structures. A back-end-of-line interconnect structure includes a first metallization level, a second metallization level, and a third metallization level arranged between the first metallization level and the second metallization level. The T-coil includes a first inductor with a first coil arranged in the first metallization level and a second inductor with a second coil arranged in the second metallization level. A peaking inductor includes a coil arranged in the third metallization level. The first coil of the first inductor, the second coil of the second inductor, and the coil of the peaking inductor are stacked in the back-end-of-line interconnect structure with an overlapping arrangement.

Abstract: Fabrication methods for a 3D multipath inductor, including forming a metal layer to form spiral turns about a center region, the spiral turns including segments that extend length-wise along the turns and having positions that vary from an innermost position and an outermost position relative to the center region; forming a lateral cross-over configured to couple portions of lateral segments in different relative positions from the center region to form lateral segment paths that have a substantially same length for all lateral segment paths in a grouping thereof; forming an additional metal layer to form spiral turns about the center region including corresponding geometry to the first metal layer; and forming a vertical cross-over configured to couple portions of segments on different metal layers to form vertical segment paths that have a substantially same length for all vertical segment paths in a grouping thereof.

Abstract: A high performance, on-chip a parallel stacked inductor which achieves a higher Q value. The inductor is formed on a layered substrate with a top metal layer having spiral winding conductive segments that terminate at an overpass junction, and a bottom metal layer traversing adjacent to, and parallel with, the top metal layer. The bottom metal layer having multiple bar vias imbedded therein for current carrying capabilities. The overpass junction having a width that is greater than the width of the adjacent spiral winding conductive segments.

Abstract: Embodiments of the present disclosure provide an integrated circuit (IC) structure including: a first conductive layer of a device structure; a second conductive layer of the device structure vertically separated from the first conductive layer, wherein a load resistor couples the second conductive layer to ground; a t-coil having a first end coupled to the first conductive layer, and a second end coupled to the second conductive layer; and a variable capacitor having a first end coupled to the first conductive layer, and a second end coupled to the second conductive layer, the variable capacitor having an adjustable capacitance.

Abstract: A high performance, on-chip a parallel stacked inductor which achieves a higher Q value. The inductor is formed on a layered substrate with a top metal layer having spiral winding conductive segments that terminate at an overpass junction, and a bottom metal layer traversing adjacent to, and parallel with, the top metal layer. The bottom metal layer having multiple bar vias imbedded therein for current carrying capabilities. The overpass junction having a width that is greater than the width of the adjacent spiral winding conductive segments.

Abstract: Structures and methods for implementing high performance symmetric multi-port inductors are provided. The multiport inductor structure includes a plurality of conductors which are structured and arranged in turns to obtain symmetry between a plurality of selected input terminals connecting to respective ones of the plurality of conductors.

Abstract: A three-dimensional multipath inductor includes turns disposed about a center region on two layers, the turns on the two layers having corresponding geometry therebetween. Each of the turns is comprised of two or more segments that extend length-wise along the turns, and the segments have positions that vary from an innermost position relative to the center region and an outermost position relative to the center region. A lateral cross-over is configured to couple the segments of at least one turn on one layer with the segments on a turn on a same layer to form segment paths that have a substantially same length for all segment paths in a grouping of segment paths on that same layer. A vertical cross-over is configured to couple the segments on different vertically stacked metal layers to have the segment groups with a substantially same length for all segment paths based on vertical lengths.

Abstract: An SPDT switch in a RF communication transceiver provides for choosing the transmit/receive path for the RF signal. It consists of the series and shunt branches each consisting of stack of FETs. Performance metrics of the RF switch are insertion loss and isolation. At high frequency, the device/FET capacitance and the parasitic capacitances provide a leakage path for the signal, resulting in higher insertion loss and lower isolation. A parallel resonant LC network across each of the series and/or shunt branch FETs in a SPDT switch provides lower insertion loss, higher switch isolation, and lower out of band harmonics when compared to that of the state of the art SPDT switch. A method to reduce the form factor of such switch configuration is disclosed which is useful in wireless front end modules.

Abstract: Structures and methods for implementing high performance symmetric multi-port inductors are provided. The multiport inductor structure includes a plurality of conductors which are structured and arranged in turns to obtain symmetry between a plurality of selected input terminals connecting to respective ones of the plurality of conductors.

Abstract: An SPDT switch in a RF communication transceiver provides for choosing the transmit/receive path for the RF signal. It consists of the series and shunt branches each consisting of stack of FETs. Performance metrics of the RF switch are insertion loss and isolation. At high frequency, the device/FET capacitance and the parasitic capacitances provide a leakage path for the signal, resulting in higher insertion loss and lower isolation. A parallel resonant LC network across each of the series and/or shunt branch FETs in a SPDT switch provides lower insertion loss, higher switch isolation, and lower out of band harmonics when compared to that of the state of the art SPDT switch. A method to reduce the form factor of such switch configuration is disclosed which is useful in wireless front end modules.