Abstract: A decoding approaching suitable for architectures such as Very Long Instruction Word (VLIW), in which throughput performance would be reduced in case if large blocks of conditional core are executed repetitively. Some of the code-words are received according to escape modes, which require different kinds of processing depending on specific mode. The decoding logic is partitioned into two parts, with the first part accessing entries in tables corresponding to code-words. The first part writes the symbol value retrieved from the accessed entry into an output buffer. In case of escape modes, the first part writes an intermediate decoded value to the output buffer, and an escape mode identifier retrieved from an accessed entry, and a position identifier in the output buffer for the symbol sought to be decoded in an intermediate buffer. The second part then performs the specific processing required for each entry in the intermediate buffer.