Patents by Inventor Venkata Ravi Shankar JONNALAGADDA

Venkata Ravi Shankar JONNALAGADDA has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method and system for generating memory maps
    Patent number: 12293081
    Abstract: The present disclosure relates to field of Dual In-Line Memory Modules that discloses method and system for generating memory maps. The method comprises detecting, by computing system, at least one of DIMM and one or more Dynamic Random Access Memory (DRAM) chips associated with computing system. The one or more accelerators are configured in at least one of DIMM and one or more DRAM chips. Further, the method includes determining accelerator information for each of one or more accelerators via at least one of Serial Presence Detect (SPD) and Multi-Purpose Register (MPR) associated with at least one of DIMM and one or more DRAM chips. Method includes generating unique memory map for each of one or more accelerators based on accelerator information of corresponding one or more accelerators. As a result, performance of computing system may be improved as accelerator capabilities of one or more accelerators are effectively utilized.
    Type: Grant
    Filed: May 2, 2023
    Date of Patent: May 6, 2025
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Raghu Vamsi Krishna Talanki, Archita Khare, Eldho P. Mathew, Jin In So, Jong-Geon Lee, Venkata Ravi Shankar Jonnalagadda, Vishnu Charan Thummala
  • METHOD AND SYSTEM FOR GENERATING MEMORY MAPS
    Publication number: 20240295963
    Abstract: The present disclosure relates to field of Dual In-Line Memory Modules that discloses method and system for generating memory maps. The method comprises detecting, by computing system, at least one of DIMM and one or more Dynamic Random Access Memory (DRAM) chips associated with computing system. The one or more accelerators are configured in at least one of DIMM and one or more DRAM chips. Further, the method includes determining accelerator information for each of one or more accelerators via at least one of Serial Presence Detect (SPD) and Multi-Purpose Register (MPR) associated with at least one of DIMM and one or more DRAM chips. Method includes generating unique memory map for each of one or more accelerators based on accelerator information of corresponding one or more accelerators. As a result, performance of computing system may be improved as accelerator capabilities of one or more accelerators are effectively utilized.
    Type: Application
    Filed: May 2, 2023
    Publication date: September 5, 2024
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Raghu Vamsi Krishna TALANKI, Archita KHARE, Eldho P. MATHEW, Jin In SO, Jong-Geon LEE, Venkata Ravi Shankar JONNALAGADDA, Vishnu Charan THUMMALA