Patents by Inventor Venkata Yaswanth Raparti

Venkata Yaswanth Raparti has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11734420
    Abstract: A snooping invalidation module is implemented at the network interface for a given core, or processing element, of a multicore or manycore device, e.g., NoC device, to discard packets with invalid header flits (e.g., duplicate packets) from being injected into the device, e.g., by a malicious hardware trojan implemented in the network interface. In some embodiments, a data-snooping detection circuit is implemented to detect a source of an on-going attack.
    Type: Grant
    Filed: May 29, 2020
    Date of Patent: August 22, 2023
    Assignee: Colorado State University Research Foundation
    Inventors: Sudeep Pasricha, Venkata Yaswanth Raparti
  • Patent number: 11698876
    Abstract: A processing device in a memory sub-system receives a plurality of requests to perform a plurality of input/output (IO) operations corresponding to a plurality of logical devices associated with a memory device and assigns the plurality of requests to respective queues associated with the plurality of logic devices. The processing device further iteratively processes the plurality of requests in view of respective numbers of operation credits associated with the plurality of logical devices, wherein the respective numbers of credits are based at least in part on respective sets of quality of service (QoS) parameters for the plurality of logical devices.
    Type: Grant
    Filed: April 5, 2022
    Date of Patent: July 11, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Horia C. Simionescu, Xiaodong Wang, Venkata Yaswanth Raparti
  • Publication number: 20220237133
    Abstract: A processing device in a memory sub-system receives a plurality of requests to perform a plurality of input/output (IO) operations corresponding to a plurality of logical devices associated with a memory device and assigns the plurality of requests to respective queues associated with the plurality of logic devices. The processing device further iteratively processes the plurality of requests in view of respective numbers of operation credits associated with the plurality of logical devices, wherein the respective numbers of credits are based at least in part on respective sets of quality of service (QoS) parameters for the plurality of logical devices.
    Type: Application
    Filed: April 5, 2022
    Publication date: July 28, 2022
    Inventors: Horia C. Simionescu, Xiaodong Wang, Venkata Yaswanth Raparti
  • Patent number: 11321257
    Abstract: A processing device in a memory sub-system iteratively processes input/output (I/O) operations corresponding to a plurality of logical devices associated with a memory device. Tor each of the plurality of logical devices, the processing includes identifying a current logical device, determining one or more I/O operations in queue for the current logical device, and determining a number of operation credits associated with the current logical device. The number of credits is based at least in part on a set of quality of service (QoS) parameters for the current logical device. The processing further includes responsive to determining that the number of operation credits satisfies a threshold condition, performing the one or more I/O operations for the current logical device and identifying a subsequent logical device of the plurality of logical devices.
    Type: Grant
    Filed: August 27, 2020
    Date of Patent: May 3, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Horia C. Simionescu, Xiaodong Wang, Venkata Yaswanth Raparti
  • Publication number: 20210200703
    Abstract: A processing device in a memory sub-system iteratively processes input/output (I/O) operations corresponding to a plurality of logical devices associated with a memory device. Tor each of the plurality of logical devices, the processing includes identifying a current logical device, determining one or more I/O operations in queue for the current logical device, and determining a number of operation credits associated with the current logical device. The number of credits is based at least in part on a set of quality of service (QoS) parameters for the current logical device. The processing further includes responsive to determining that the number of operation credits satisfies a threshold condition, performing the one or more I/O operations for the current logical device and identifying a subsequent logical device of the plurality of logical devices.
    Type: Application
    Filed: August 27, 2020
    Publication date: July 1, 2021
    Inventors: Horia C. Simionescu, Xiaodong Wang, Venkata Yaswanth Raparti
  • Publication number: 20200380121
    Abstract: A snooping invalidation module is implemented at the network interface for a given core, or processing element, of a multicore or manycore device, e.g., NoC device, to discard packets with invalid header flits (e.g., duplicate packets) from being injected into the device, e.g., by a malicious hardware trojan implemented in the network interface. In some embodiments, a data-snooping detection circuit is implemented to detect a source of an on-going attack.
    Type: Application
    Filed: May 29, 2020
    Publication date: December 3, 2020
    Inventors: Sudeep Pasricha, Venkata Yaswanth Raparti