Patents by Inventor Venkatachaiam C. Jaiprakash

Venkatachaiam C. Jaiprakash has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6518616
    Abstract: A method for a memory cell has a trench capacitor and a vertical transistor adjacent to the capacitor. The vertical transistor has a gate conductor above the trench capacitor. The upper portion of the gate conductor is narrower than the lower portion of the gate conductor. The memory cell further includes spacers adjacent the upper portion of the gate conductor and a bitline contact adjacent to the gate conductor. The spacers reduce short circuits between the bitline contact and the gate conductor. The gate contact above the gate conductor has an insulator which separates the gate contact from the bitline. The difference between the width of the upper and lower portions of the gate conductor reduces short circuits between the bitline contact and the gate conductor.
    Type: Grant
    Filed: April 18, 2001
    Date of Patent: February 11, 2003
    Assignees: International Business Machines Corporation, Infineon Technologies AG
    Inventors: Thomas W. Dyer, Stephan P. Kudelka, Venkatachaiam C. Jaiprakash, Carl J. Radens
  • Publication number: 20020155654
    Abstract: A method for a memory cell has a trench capacitor and a vertical transistor adjacent to the capacitor. The vertical transistor has a gate conductor above the trench capacitor. The upper portion of the gate conductor is narrower than the lower portion of the gate conductor. The memory cell further includes spacers adjacent the upper portion of the gate conductor and a bitline contact adjacent to the gate conductor. The spacers reduce short circuits between the bitline contact and the gate conductor. The gate contact above the gate conductor has an insulator which separates the gate contact from the bitline. The difference between the width of the upper and lower portions of the gate conductor reduces short circuits between the bitline contact and the gate conductor.
    Type: Application
    Filed: April 18, 2001
    Publication date: October 24, 2002
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Thomas W. Dyer, Stephan P. Kudelka, Venkatachaiam C. Jaiprakash, Carl J. Radens