Patents by Inventor Venkataraghavan Punnapakkam Krishnan

Venkataraghavan Punnapakkam Krishnan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Digital architecture for DFT/IDFT hardware
    Patent number: 8484278
    Abstract: Embodiments of the present invention can provide circuits and systems for computing a discrete Fourier transform (DFT) or an inverse discrete Fourier transform (IDFT). An embodiment includes an input circuit, an intermediate circuit, an output circuit, and an accumulator circuit. The input circuit can receive a set of input values, and can use a first set of degenerate rotators to generate a first set of intermediate values. The intermediate circuit can receive the first set of intermediate values, and can use a set of CORDICs (coordinate rotation digital computers) to generate a second set of intermediate values. The output circuit can receive the second set of intermediate values, and can use a second set of degenerate rotators to generate a third set of intermediate values. The accumulator circuit can receive the third set of intermediate values, and can use a set of accumulators to generate a set of output values.
    Type: Grant
    Filed: May 11, 2007
    Date of Patent: July 9, 2013
    Assignee: Synopsys, Inc.
    Inventors: Baijayanta Ray, Venkataraghavan Punnapakkam Krishnan, Sriram Balasubramanian, Dalavaipatnam Rangarao Seetharaman
  • Digital architecture for DFT/IDFT hardware
    Publication number: 20080281894
    Abstract: Embodiments of the present invention can provide circuits and systems for computing a discrete Fourier transform (DFT) or an inverse discrete Fourier transform (IDFT). An embodiment includes an input circuit, an intermediate circuit, an output circuit, and an accumulator circuit. The input circuit can receive a set of input values, and can use a first set of degenerate rotators to generate a first set of intermediate values. The intermediate circuit can receive the first set of intermediate values, and can use a set of CORDICs (coordinate rotation digital computers) to generate a second set of intermediate values. The output circuit can receive the second set of intermediate values, and can use a second set of degenerate rotators to generate a third set of intermediate values. The accumulator circuit can receive the third set of intermediate values, and can use a set of accumulators to generate a set of output values.
    Type: Application
    Filed: May 11, 2007
    Publication date: November 13, 2008
    Inventors: Baijayanta Ray, Venkataraghavan Punnapakkam Krishnan, Sriram Balasubramanian, Dalavaipatnam Rangarao Seetharaman