Patents by Inventor Venkatasubramani Balu
Venkatasubramani Balu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11935972Abstract: Tri-layer semiconductor stacks for patterning features on solar cells, and the resulting solar cells, are described herein. In an example, a solar cell includes a substrate. A semiconductor structure is disposed above the substrate. The semiconductor structure includes a P-type semiconductor layer disposed directly on a first semiconductor layer. A third semiconductor layer is disposed directly on the P-type semiconductor layer. An outermost edge of the third semiconductor layer is laterally recessed from an outermost edge of the first semiconductor layer by a width. An outermost edge of the P-type semiconductor layer is sloped from the outermost edge of the third semiconductor layer to the outermost edge of the third semiconductor layer. A conductive contact structure is electrically connected to the semiconductor structure.Type: GrantFiled: May 6, 2022Date of Patent: March 19, 2024Assignee: Maxeon Solar Pte. Ltd.Inventors: Kieran Mark Tracy, David D. Smith, Venkatasubramani Balu, Asnat Masad, Ann Waldhauer
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Patent number: 11502208Abstract: Methods of fabricating solar cell emitter regions with differentiated P-type and N-type regions architectures, and resulting solar cells, are described. In an example, a back contact solar cell includes a substrate having a light-receiving surface and a back surface. A first polycrystalline silicon emitter region of a first conductivity type is disposed on a first thin dielectric layer disposed on the back surface of the substrate. A second polycrystalline silicon emitter region of a second, different, conductivity type is disposed on a second thin dielectric layer disposed on the back surface of the substrate. A third thin dielectric layer is disposed laterally directly between the first and second polycrystalline silicon emitter regions. A first conductive contact structure is disposed on the first polycrystalline silicon emitter region. A second conductive contact structure is disposed on the second polycrystalline silicon emitter region.Type: GrantFiled: November 8, 2019Date of Patent: November 15, 2022Assignee: SunPower CorporationInventors: Seung Bum Rim, David D. Smith, Taiqing Qiu, Staffan Westerberg, Kieran Mark Tracy, Venkatasubramani Balu
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Patent number: 11437530Abstract: Methods of fabricating solar cell emitter regions with differentiated P-type and N-type regions architectures, and resulting solar cells, are described. In an example, a back contact solar cell can include a substrate having a light-receiving surface and a back surface. A first polycrystalline silicon emitter region of a first conductivity type is disposed on a first thin dielectric layer disposed on the back surface of the substrate. A second polycrystalline silicon emitter region of a second, different, conductivity type is disposed on a second thin dielectric layer disposed on the back surface of the substrate. A third thin dielectric layer is disposed over an exposed outer portion of the first polycrystalline silicon emitter region and is disposed laterally directly between the first and second polycrystalline silicon emitter regions. A first conductive contact structure is disposed on the first polycrystalline silicon emitter region.Type: GrantFiled: March 4, 2019Date of Patent: September 6, 2022Assignee: SunPower CorporationInventors: David D. Smith, Timothy Weidman, Scott Harrington, Venkatasubramani Balu
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Publication number: 20220262966Abstract: Tri-layer semiconductor stacks for patterning features on solar cells, and the resulting solar cells, are described herein. In an example, a solar cell includes a substrate. A semiconductor structure is disposed above the substrate. The semiconductor structure includes a P-type semiconductor layer disposed directly on a first semiconductor layer. A third semiconductor layer is disposed directly on the P-type semiconductor layer. An outermost edge of the third semiconductor layer is laterally recessed from an outermost edge of the first semiconductor layer by a width. An outermost edge of the P-type semiconductor layer is sloped from the outermost edge of the third semiconductor layer to the outermost edge of the third semiconductor layer. A conductive contact structure is electrically connected to the semiconductor structure.Type: ApplicationFiled: May 6, 2022Publication date: August 18, 2022Inventors: Kieran Mark Tracy, David D. Smith, Venkatasubramani Balu, Asnat Masad, Ann Waldhauer
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Patent number: 11355654Abstract: Tri-layer semiconductor stacks for patterning features on solar cells, and the resulting solar cells, are described herein. In an example, a solar cell includes a substrate. A semiconductor structure is disposed above the substrate. The semiconductor structure includes a P-type semiconductor layer disposed directly on a first semiconductor layer. A third semiconductor layer is disposed directly on the P-type semiconductor layer. An outermost edge of the third semiconductor layer is laterally recessed from an outermost edge of the first semiconductor layer by a width. An outermost edge of the P-type semiconductor layer is sloped from the outermost edge of the third semiconductor layer to the outermost edge of the third semiconductor layer. A conductive contact structure is electrically connected to the semiconductor structure.Type: GrantFiled: December 9, 2019Date of Patent: June 7, 2022Assignee: SunPower CorporationInventors: Kieran Mark Tracy, David D. Smith, Venkatasubramani Balu, Asnat Masad, Ann Waldhauer
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Patent number: 10950740Abstract: Methods of fabricating solar cell emitter regions with differentiated P-type and N-type region architectures, and the resulting solar cells, are described herein. In an example, a solar cell includes an N-type semiconductor substrate having a light-receiving surface and a back surface. A plurality of N-type polycrystalline silicon regions is disposed on a first thin dielectric layer disposed on the back surface of the N-type semiconductor substrate. A plurality of P-type polycrystalline silicon regions is disposed on a second thin dielectric layer disposed in a corresponding one of a plurality of trenches interleaving the plurality of N-type polycrystalline silicon regions in the back surface of the N-type semiconductor substrate.Type: GrantFiled: November 26, 2018Date of Patent: March 16, 2021Assignee: SunPower CorporationInventors: David D. Smith, Ann Waldhauer, Venkatasubramani Balu, Kieran Mark Tracy
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Publication number: 20200119220Abstract: Tri-layer semiconductor stacks for patterning features on solar cells, and the resulting solar cells, are described herein. In an example, a solar cell includes a substrate. A semiconductor structure is disposed above the substrate. The semiconductor structure includes a P-type semiconductor layer disposed directly on a first semiconductor layer. A third semiconductor layer is disposed directly on the P-type semiconductor layer. An outermost edge of the third semiconductor layer is laterally recessed from an outermost edge of the first semiconductor layer by a width. An outermost edge of the P-type semiconductor layer is sloped from the outermost edge of the third semiconductor layer to the outermost edge of the third semiconductor layer. A conductive contact structure is electrically connected to the semiconductor structure.Type: ApplicationFiled: December 9, 2019Publication date: April 16, 2020Inventors: Kieran Mark Tracy, David D. Smith, Venkatasubramani Balu, Asnat Masad, Ann Waldhauer
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Publication number: 20200075784Abstract: Methods of fabricating solar cell emitter regions with differentiated P-type and N-type regions architectures, and resulting solar cells, are described. In an example, a back contact solar cell includes a substrate having a light-receiving surface and a back surface. A first polycrystalline silicon emitter region of a first conductivity type is disposed on a first thin dielectric layer disposed on the back surface of the substrate. A second polycrystalline silicon emitter region of a second, different, conductivity type is disposed on a second thin dielectric layer disposed on the back surface of the substrate. A third thin dielectric layer is disposed laterally directly between the first and second polycrystalline silicon emitter regions. A first conductive contact structure is disposed on the first polycrystalline silicon emitter region. A second conductive contact structure is disposed on the second polycrystalline silicon emitter region.Type: ApplicationFiled: November 8, 2019Publication date: March 5, 2020Inventors: Seung Bum Rim, David D. Smith, Taiqing Qiu, Staffan Westerberg, Kieran Mark Tracy, Venkatasubramani Balu
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Patent number: 10505068Abstract: Tri-layer semiconductor stacks for patterning features on solar cells, and the resulting solar cells, are described herein. In an example, a solar cell includes a substrate. A semiconductor structure is disposed above the substrate. The semiconductor structure includes a P-type semiconductor layer disposed directly on a first semiconductor layer. A third semiconductor layer is disposed directly on the P-type semiconductor layer. An outermost edge of the third semiconductor layer is laterally recessed from an outermost edge of the first semiconductor layer by a width. An outermost edge of the P-type semiconductor layer is sloped from the outermost edge of the third semiconductor layer to the outermost edge of the third semiconductor layer. A conductive contact structure is electrically connected to the semiconductor structure.Type: GrantFiled: February 25, 2019Date of Patent: December 10, 2019Assignee: SunPower CorporationInventors: Kieran Mark Tracy, David D. Smith, Venkatasubramani Balu, Asnat Masad, Ann Waldhauer
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Publication number: 20190267499Abstract: Methods of fabricating solar cell emitter regions with differentiated P-type and N-type regions architectures, and resulting solar cells, are described. In an example, a back contact solar cell can include a substrate having a light-receiving surface and a back surface. A first polycrystalline silicon emitter region of a first conductivity type is disposed on a first thin dielectric layer disposed on the back surface of the substrate. A second polycrystalline silicon emitter region of a second, different, conductivity type is disposed on a second thin dielectric layer disposed on the back surface of the substrate. A third thin dielectric layer is disposed over an exposed outer portion of the first polycrystalline silicon emitter region and is disposed laterally directly between the first and second polycrystalline silicon emitter regions. A first conductive contact structure is disposed on the first polycrystalline silicon emitter region.Type: ApplicationFiled: March 4, 2019Publication date: August 29, 2019Inventors: David D. Smith, Timothy Weidman, Scott Harrington, Venkatasubramani Balu
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Publication number: 20190207040Abstract: Chemical polishing of solar cell surfaces and the resulting structures are described herein. In an example, a method of fabricating a solar cell includes texturizing both first side and second side surfaces of a silicon substrate with a first hydroxide-based etch process. The method also includes reducing a surface roughness factor of the texturized second side surface of the silicon substrate with a second hydroxide-based etch process. The method also includes, subsequent to reducing the surface roughness factor of the texturized second side surface of the silicon substrate, forming emitter regions on the second side surface of the silicon substrate.Type: ApplicationFiled: December 29, 2017Publication date: July 4, 2019Inventors: Scott HARRINGTON, Amada MONTESDEOCA SANTANA, Venkatasubramani BALU
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Publication number: 20190189813Abstract: Tri-layer semiconductor stacks for patterning features on solar cells, and the resulting solar cells, are described herein. In an example, a solar cell includes a substrate. A semiconductor structure is disposed above the substrate. The semiconductor structure includes a P-type semiconductor layer disposed directly on a first semiconductor layer. A third semiconductor layer is disposed directly on the P-type semiconductor layer. An outermost edge of the third semiconductor layer is laterally recessed from an outermost edge of the first semiconductor layer by a width. An outermost edge of the P-type semiconductor layer is sloped from the outermost edge of the third semiconductor layer to the outermost edge of the third semiconductor layer. A conductive contact structure is electrically connected to the semiconductor structure.Type: ApplicationFiled: February 25, 2019Publication date: June 20, 2019Inventors: Kieran Mark Tracy, David D. Smith, Venkatasubramani Balu, Asnat Masad, Ann Waldhauer
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Publication number: 20190097068Abstract: Methods of fabricating solar cell emitter regions with differentiated P-type and N-type region architectures, and the resulting solar cells, are described herein. In an example, a solar cell includes an N-type semiconductor substrate having a light-receiving surface and a back surface. A plurality of N-type polycrystalline silicon regions is disposed on a first thin dielectric layer disposed on the back surface of the N-type semiconductor substrate. A plurality of P-type polycrystalline silicon regions is disposed on a second thin dielectric layer disposed in a corresponding one of a plurality of trenches interleaving the plurality of N-type polycrystalline silicon regions in the back surface of the N-type semiconductor substrate.Type: ApplicationFiled: November 26, 2018Publication date: March 28, 2019Inventors: David D. Smith, Ann Waldhauer, Venkatasubramani Balu, Kieran Mark Tracy
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Patent number: 10224442Abstract: Methods of fabricating solar cell emitter regions with differentiated P-type and N-type regions architectures, and resulting solar cells, are described. In an example, a back contact solar cell can include a substrate having a light-receiving surface and a back surface. A first polycrystalline silicon emitter region of a first conductivity type is disposed on a first thin dielectric layer disposed on the back surface of the substrate. A second polycrystalline silicon emitter region of a second, different, conductivity type is disposed on a second thin dielectric layer disposed on the back surface of the substrate. A third thin dielectric layer is disposed over an exposed outer portion of the first polycrystalline silicon emitter region and is disposed laterally directly between the first and second polycrystalline silicon emitter regions. A first conductive contact structure is disposed on the first polycrystalline silicon emitter region.Type: GrantFiled: October 26, 2016Date of Patent: March 5, 2019Assignee: SunPower CorporationInventors: David D. Smith, Timothy Weidman, Scott Harrington, Venkatasubramani Balu
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Patent number: 10217878Abstract: Tri-layer semiconductor stacks for patterning features on solar cells, and the resulting solar cells, are described herein. In an example, a solar cell includes a substrate. A semiconductor structure is disposed above the substrate. The semiconductor structure includes a P-type semiconductor layer disposed directly on a first semiconductor layer. A third semiconductor layer is disposed directly on the P-type semiconductor layer. An outermost edge of the third semiconductor layer is laterally recessed from an outermost edge of the first semiconductor layer by a width. An outermost edge of the P-type semiconductor layer is sloped from the outermost edge of the third semiconductor layer to the outermost edge of the third semiconductor layer. A conductive contact structure is electrically connected to the semiconductor structure.Type: GrantFiled: April 1, 2016Date of Patent: February 26, 2019Assignee: SunPower CorporationInventors: Kieran Mark Tracy, David D. Smith, Venkatasubramani Balu, Asnat Masad, Ann Waldhauer
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Patent number: 10141462Abstract: Methods of fabricating solar cell emitter regions with differentiated P-type and N-type region architectures, and the resulting solar cells, are described herein. In an example, a solar cell includes an N-type semiconductor substrate having a light-receiving surface and a back surface. A plurality of N-type polycrystalline silicon regions is disposed on a first thin dielectric layer disposed on the back surface of the N-type semiconductor substrate. A plurality of P-type polycrystalline silicon regions is disposed on a second thin dielectric layer disposed in a corresponding one of a plurality of trenches interleaving the plurality of N-type polycrystalline silicon regions in the back surface of the N-type semiconductor substrate.Type: GrantFiled: December 19, 2016Date of Patent: November 27, 2018Assignee: SunPower CorporationInventors: David D. Smith, Ann Waldhauer, Venkatasubramani Balu, Kieran Mark Tracy
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Publication number: 20180175221Abstract: Methods of fabricating solar cell emitter regions with differentiated P-type and N-type region architectures, and the resulting solar cells, are described herein. In an example, a solar cell includes an N-type semiconductor substrate having a light-receiving surface and a back surface. A plurality of N-type polycrystalline silicon regions is disposed on a first thin dielectric layer disposed on the back surface of the N-type semiconductor substrate. A plurality of P-type polycrystalline silicon regions is disposed on a second thin dielectric layer disposed in a corresponding one of a plurality of trenches interleaving the plurality of N-type polycrystalline silicon regions in the back surface of the N-type semiconductor substrate.Type: ApplicationFiled: December 19, 2016Publication date: June 21, 2018Inventors: David D. Smith, Ann Waldhauer, Venkatasubramani Balu, Kieran Mark Tracy
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Patent number: 9837259Abstract: A method of processing a silicon substrate can include etching the silicon substrate with a first etchant having a first concentration and etching with a second etchant having a second concentration. In an embodiment, the second concentration of the second etchant can be greater than the first concentration of the first etchant. In one embodiment, the first etchant can be a different type of etchant than the second etchant. In an embodiment, the first and second etchant can be the same type of etchant. In some embodiments the silicon substrate can be cleaned with a first cleaning solution to remove contaminants from the silicon substrate prior to etching with the first etchant. In an embodiment, the silicon substrate can be cleaned with a second cleaning solution after etching the silicon substrate with a second etchant.Type: GrantFiled: August 29, 2014Date of Patent: December 5, 2017Assignees: SunPower Corporation, Total Marketing ServicesInventors: Scott Harrington, Venkatasubramani Balu, Amada Lorena Montesdeoca Santana
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Publication number: 20170288070Abstract: Tri-layer semiconductor stacks for patterning features on solar cells, and the resulting solar cells, are described herein. In an example, a solar cell includes a substrate. A semiconductor structure is disposed above the substrate. The semiconductor structure includes a P-type semiconductor layer disposed directly on a first semiconductor layer. A third semiconductor layer is disposed directly on the P-type semiconductor layer. An outermost edge of the third semiconductor layer is laterally recessed from an outermost edge of the first semiconductor layer by a width. An outermost edge of the P-type semiconductor layer is sloped from the outermost edge of the third semiconductor layer to the outermost edge of the third semiconductor layer. A conductive contact structure is electrically connected to the semiconductor structure.Type: ApplicationFiled: April 1, 2016Publication date: October 5, 2017Inventors: Kieran Mark Tracy, David D. Smith, Venkatasubramani Balu, Asnat Masad, Ann Waldhauer
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Publication number: 20170288074Abstract: Methods of fabricating solar cell emitter regions with differentiated P-type and N-type regions architectures, and resulting solar cells, are described. In an example, a back contact solar cell can include a substrate having a light-receiving surface and a back surface. A first polycrystalline silicon emitter region of a first conductivity type is disposed on a first thin dielectric layer disposed on the back surface of the substrate. A second polycrystalline silicon emitter region of a second, different, conductivity type is disposed on a second thin dielectric layer disposed on the back surface of the substrate. A third thin dielectric layer is disposed over an exposed outer portion of the first polycrystalline silicon emitter region and is disposed laterally directly between the first and second polycrystalline silicon emitter regions. A first conductive contact structure is disposed on the first polycrystalline silicon emitter region.Type: ApplicationFiled: October 26, 2016Publication date: October 5, 2017Inventors: David D. Smith, Timothy Weidman, Scott Harrington, Venkatasubramani Balu