Patents by Inventor Venkatasubramanyam Visvanathan

Venkatasubramanyam Visvanathan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method for designing a semiconductor device based on leakage current estimation
    Patent number: 8296701
    Abstract: A method of designing a semiconductor device includes preparing a first design for a semiconductor device and estimating leakage current for the first design. The method also includes determining a leakage current cumulative distribution function (CDF) for the first design. The method further includes preparing a second design for the semiconductor device based on determination of the leakage current CDF for the first design. Further, the method includes estimating leakage current for the second design. The method also includes determining a leakage current CDF for the second design in accordance to the determination of the leakage current CDF for the first design. Moreover, the method includes selecting one of the first design and the second design based on a comparison of the leakage current CDF for the first design and the leakage CDF for the second design.
    Type: Grant
    Filed: December 28, 2010
    Date of Patent: October 23, 2012
    Assignee: Texas Instruments Incorporated
    Inventors: Palkesh Jain, Ajoy Mandal, Arvind Nembili Veeravalli, Venkatasubramanyam Visvanathan
  • Facilitating high-level validation of integrated circuits in parallel with development of blocks in a hierarchical design approach
    Patent number: 7275223
    Abstract: A design management tool which automates the parallel validation of an entire integrated circuit while the individual blocks (together forming the integrated circuit) are designed. In an embodiment, a designer specifies various checkpoints associated with each design stage, and the specific information to be made available to a top level performing the validation. When each checkpoint is reached for a design block, the specified information is made available to the top level and the validation of the integrated circuit is performed up to that checkpoint. As a result, design closure of the integrated circuit can be obtained quickly.
    Type: Grant
    Filed: July 1, 2005
    Date of Patent: September 25, 2007
    Assignee: Texas Instruments Incorporated
    Inventors: Venkatasubramanyam Visvanathan, Sharad Arora, Sivakumar Ramaiyan
  • Facilitating High Level Validation of Integrated Circuits in Parallel with Development of Blocks in a Hierarchical Design Approach
    Publication number: 20060265673
    Abstract: A design management tool which automates the parallel validation of an entire integrated circuit while the individual blocks (together forming the integrated circuit) are designed. In an embodiment, a designer specifies various checkpoints associated with each design stage, and the specific information to be made available to a top level performing the validation. When each checkpoint is reached for a design block, the specified information is made available to the top level and the validation of the integrated circuit is performed up to that checkpoint. As a result, design closure of the integrated circuit can be obtained quickly.
    Type: Application
    Filed: July 1, 2005
    Publication date: November 23, 2006
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Venkatasubramanyam Visvanathan, Sharad ARORA, Sivakumar RAMAIYAN