Patents by Inventor Venkatesan Ananthan
Venkatesan Ananthan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9373716Abstract: Impact ionization devices including vertical and recessed impact ionization metal oxide semiconductor field effect transistor (MOSFET) devices and methods of forming such devices are disclosed. The devices require lower threshold voltage than conventional MOSFET devices while maintaining a footprint equal to or less than conventional MOSFET devices.Type: GrantFiled: January 27, 2014Date of Patent: June 21, 2016Assignee: Micron Technology, Inc.Inventor: Venkatesan Ananthan
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Publication number: 20150145044Abstract: The invention includes floating body transistor constructions containing U-shaped semiconductor material slices. The U-shapes have a pair of prongs joined to a central portion. Each of the prongs contains a source/drain region of a pair of gatedly-coupled source/drain regions, and the floating bodies of the transistors are within the central portions. The semiconductor material slices can be between front gates and back gates. The floating body transistor constructions can be incorporated into memory arrays, which in turn can be incorporated into electronic systems. The invention also includes methods of forming floating body transistor constructions, and methods of incorporating floating body transistor constructions into memory arrays.Type: ApplicationFiled: January 22, 2015Publication date: May 28, 2015Inventors: Sanh D. Tang, Venkatesan Ananthan
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Patent number: 8946815Abstract: The invention includes floating body transistor constructions containing U-shaped semiconductor material slices. The U-shapes have a pair of prongs joined to a central portion. Each of the prongs contains a source/drain region of a pair of gatedly-coupled source/drain regions, and the floating bodies of the transistors are within the central portions. The semiconductor material slices can be between front gates and back gates. The floating body transistor constructions can be incorporated into memory arrays, which in turn can be incorporated into electronic systems. The invention also includes methods of forming floating body transistor constructions, and methods of incorporating floating body transistor constructions into memory arrays.Type: GrantFiled: August 5, 2013Date of Patent: February 3, 2015Assignee: Micron Technology, Inc.Inventors: Sanh D. Tang, Venkatesan Ananthan
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Publication number: 20140138766Abstract: Impact ionization devices including vertical and recessed impact ionization metal oxide semiconductor field effect transistor (MOSFET) devices and methods of forming such devices are disclosed. The devices require lower threshold voltage than conventional MOSFET devices while maintaining a footprint equal to or less than conventional MOSFET devices.Type: ApplicationFiled: January 27, 2014Publication date: May 22, 2014Applicant: Micron Technology, Inc.Inventor: Venkatesan Ananthan
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Patent number: 8710583Abstract: A recessed access device having a gate electrode formed of two or more gate materials having different work functions may reduce the gate-induced drain leakage current losses from the recessed access device. The gate electrode may include a first gate material having a high work function disposed in a bottom portion of the recessed access device and a second gate material having a lower work function disposed over the first gate material and in an upper portion of the recessed access device.Type: GrantFiled: August 2, 2011Date of Patent: April 29, 2014Assignee: Micron Technology, Inc.Inventors: Venkatesan Ananthan, Sanh D. Tang
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Patent number: 8674434Abstract: Impact ionization devices including vertical and recessed impact ionization metal oxide semiconductor field effect transistor (MOSFET) devices and methods of forming such devices are disclosed. The devices require lower threshold voltage than conventional MOSET devices while maintaining a footprint equal to or less than conventional MOSFET devices.Type: GrantFiled: March 24, 2008Date of Patent: March 18, 2014Assignee: Micron Technology, Inc.Inventor: Venkatesan Ananthan
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Publication number: 20130320440Abstract: The invention includes floating body transistor constructions containing U-shaped semiconductor material slices. The U-shapes have a pair of prongs joined to a central portion. Each of the prongs contains a source/drain region of a pair of gatedly-coupled source/drain regions, and the floating bodies of the transistors are within the central portions. The semiconductor material slices can be between front gates and back gates. The floating body transistor constructions can be incorporated into memory arrays, which in turn can be incorporated into electronic systems. The invention also includes methods of forming floating body transistor constructions, and methods of incorporating floating body transistor constructions into memory arrays.Type: ApplicationFiled: August 5, 2013Publication date: December 5, 2013Applicant: Micron Technology, Inc.Inventors: Sanh D. Tang, Venkatesan Ananthan
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Patent number: 8501581Abstract: The invention includes floating body transistor constructions containing U-shaped semiconductor material slices. The U-shapes have a pair of prongs joined to a central portion. Each of the prongs contains a source/drain region of a pair of gatedly-coupled source/drain regions, and the floating bodies of the transistors are within the central portions. The semiconductor material slices can be between front gates and back gates. The floating body transistor constructions can be incorporated into memory arrays, which in turn can be incorporated into electronic systems. The invention also includes methods of forming floating body transistor constructions, and methods of incorporating floating body transistor constructions into memory arrays.Type: GrantFiled: March 29, 2006Date of Patent: August 6, 2013Assignee: Micron Technology, Inc.Inventors: Sanh D. Tang, Venkatesan Ananthan
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Patent number: 8368139Abstract: A method for forming an opening within a semiconductor material comprises forming a neck portion, a rounded portion below the neck portion and, in some embodiments, a protruding portion below the rounded portion. This opening may be filled with a conductor, a dielectric, or both. Embodiments to form a transistor gate, shallow trench isolation, and an isolation material separating a transistor source and drain are disclosed. Device structures formed by the method are also described.Type: GrantFiled: December 6, 2011Date of Patent: February 5, 2013Assignee: Micron Technology, Inc.Inventor: Venkatesan Ananthan
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Publication number: 20120112272Abstract: A method for forming an opening within a semiconductor material comprises forming a neck portion, a rounded portion below the neck portion and, in some embodiments, a protruding portion below the rounded portion. This opening may be filled with a conductor, a dielectric, or both. Embodiments to form a transistor gate, shallow trench isolation, and an isolation material separating a transistor source and drain are disclosed. Device structures formed by the method are also described.Type: ApplicationFiled: December 6, 2011Publication date: May 10, 2012Applicant: Micron Technology, Inc.Inventor: Venkatesan Ananthan
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Patent number: 8169032Abstract: The invention includes methods of forming PMOS transistors and NMOS transistors. The NMOS transistors can be formed to have a thin silicon-containing material between a pair of metal nitride materials, while the PMOS transistors are formed to have the metal nitride materials directly against one another. The invention also includes constructions which contain an NMOS transistor gate stack having a thin silicon-containing material between a pair of metal nitride materials. The silicon-containing material can, for example, consist of silicon, conductively-doped silicon, or silicon oxide; and can have a thickness of less than or equal to about 30 angstroms.Type: GrantFiled: November 2, 2010Date of Patent: May 1, 2012Assignee: Micron Technology, Inc.Inventors: D. V. Nirmal Ramaswamy, Venkatesan Ananthan
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Publication number: 20120032257Abstract: A recessed access device having a gate electrode formed of two or more gate materials having different work functions may reduce the gate-induced drain leakage current losses from the recessed access device. The gate electrode may include a first gate material having a high work function disposed in a bottom portion of the recessed access device and a second gate material having a lower work function disposed over the first gate material and in an upper portion of the recessed access device.Type: ApplicationFiled: August 2, 2011Publication date: February 9, 2012Applicant: MICRON TECHNOLOGY, INC.Inventors: Venkatesan Ananthan, Sanh D. Tang
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Patent number: 8008144Abstract: A recessed access device having a gate electrode formed of two or more gate materials having different work functions may reduce the gate-induced drain leakage current losses from the recessed access device. The gate electrode may include a first gate material having a high work function disposed in a bottom portion of the recessed access device and a second gate material having a lower work function disposed over the first gate material and in an upper portion of the recessed access device.Type: GrantFiled: May 11, 2006Date of Patent: August 30, 2011Assignee: Micron Technology, Inc.Inventors: Venkatesan Ananthan, Sanh D. Tang
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Publication number: 20110042754Abstract: The invention includes methods of forming PMOS transistors and NMOS transistors. The NMOS transistors can be formed to have a thin silicon-containing material between a pair of metal nitride materials, while the PMOS transistors are formed to have the metal nitride materials directly against one another. The invention also includes constructions which contain an NMOS transistor gate stack having a thin silicon-containing material between a pair of metal nitride materials. The silicon-containing material can, for example, consist of silicon, conductively-doped silicon, or silicon oxide; and can have a thickness of less than or equal to about 30 angstroms.Type: ApplicationFiled: November 2, 2010Publication date: February 24, 2011Applicant: MICRON TECHNOLOGY, INC.Inventors: D.V. Nirmal Ramaswamy, Venkatesan Ananthan
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Publication number: 20110006365Abstract: A method for forming an opening within a semiconductor material comprises forming a neck portion, a rounded portion below the neck portion and, in some embodiments, a protruding portion below the rounded portion. This opening may be filled with a conductor, a dielectric, or both. Embodiments to form a transistor gate, shallow trench isolation, and an isolation material separating a transistor source and drain are disclosed. Device structures formed by the method are also described.Type: ApplicationFiled: September 8, 2010Publication date: January 13, 2011Applicant: MICRON TECHNOLOGY, INC.Inventor: Venkatesan Ananthan
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Patent number: 7851869Abstract: The invention includes methods of forming PMOS transistors and NMOS transistors. The NMOS transistors can be formed to have a thin silicon-containing material between a pair of metal nitride materials, while the PMOS transistors are formed to have the metal nitride materials directly against one another. The invention also includes constructions which contain an NMOS transistor gate stack having a thin silicon-containing material between a pair of metal nitride materials. The silicon-containing material can, for example, consist of silicon, conductively-doped silicon, or silicon oxide; and can have a thickness of less than or equal to about 30 angstroms.Type: GrantFiled: April 28, 2009Date of Patent: December 14, 2010Assignee: Micron Technology, Inc.Inventors: D. V. Nirmal Ramaswamy, Venkatesan Ananthan
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Patent number: 7816216Abstract: A method for forming an opening within a semiconductor material comprises forming a neck portion, a rounded portion below the neck portion and, in some embodiments, a protruding portion below the rounded portion. This opening may be filled with a conductor, a dielectric, or both. Embodiments to form a transistor gate, shallow trench isolation, and an isolation material separating a transistor source and drain are disclosed. Device structures formed by the method are also described.Type: GrantFiled: July 9, 2007Date of Patent: October 19, 2010Assignee: Micron Technology, Inc.Inventor: Venkatesan Ananthan
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Publication number: 20090236657Abstract: Impact ionization devices including vertical and recessed impact ionization metal oxide semiconductor field effect transistor (MOSFET) devices and methods of forming such devices are disclosed. The devices require lower threshold voltage than conventional MOSET devices while maintaining a footprint equal to or less than conventional MOSFET devices.Type: ApplicationFiled: March 24, 2008Publication date: September 24, 2009Applicant: MICRON TECHNOLOGY, INC.Inventor: Venkatesan Ananthan
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Publication number: 20090206418Abstract: The invention includes methods of forming PMOS transistors and NMOS transistors. The NMOS transistors can be formed to have a thin silicon-containing material between a pair of metal nitride materials, while the PMOS transistors are formed to have the metal nitride materials directly against one another. The invention also includes constructions which contain an NMOS transistor gate stack having a thin silicon-containing material between a pair of metal nitride materials. The silicon-containing material can, for example, consist of silicon, conductively-doped silicon, or silicon oxide; and can have a thickness of less than or equal to about 30 angstroms.Type: ApplicationFiled: April 28, 2009Publication date: August 20, 2009Applicant: MICRON TECHNOLOGY, INC.Inventors: D.V. Nirmal Ramaswamy, Venkatesan Ananthan
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Patent number: 7544559Abstract: The invention includes methods of forming PMOS transistors and NMOS transistors. The NMOS transistors can be formed to have a thin silicon-containing material between a pair of metal nitride materials, while the PMOS transistors are formed to have the metal nitride materials directly against one another. The invention also includes constructions which contain an NMOS transistor gate stack having a thin silicon-containing material between a pair of metal nitride materials. The silicon-containing material can, for example, consist of silicon, conductively-doped silicon, or silicon oxide; and can have a thickness of less than or equal to about 30 angstroms.Type: GrantFiled: March 7, 2006Date of Patent: June 9, 2009Assignee: Micron Technolog, Inc.Inventors: D. V. Nirmal Ramaswamy, Venkatesan Ananthan