Patents by Inventor Venkatesh ANANDPADMANABHAN

Venkatesh ANANDPADMANABHAN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • LATENCY REDUCTION USING STREAM CACHE
    Publication number: 20240086330
    Abstract: A system and method for a memory sub-system to reduce latency by prefetching data blocks and preloading them into host memory of a host system. An example system including a memory device and a processing device, operatively coupled with the memory device, to perform operations including: receiving a request of a host system to access a data block in the memory device; determining the data block stored in a first buffer in host memory is related to a set of one or more data blocks stored at the memory device; and storing the set of one or more data blocks in a second buffer in the host memory, wherein the first buffer is controlled by the host system and the second buffer is controlled by a memory sub-system.
    Type: Application
    Filed: November 13, 2023
    Publication date: March 14, 2024
    Inventors: Muthazhagan BALASUBRAMANI, Venkatesh ANANDPADMANABHAN
  • Latency reduction using stream cache
    Patent number: 11816035
    Abstract: A system and method for a memory sub-system to reduce latency by prefetching data blocks and preloading them into host memory of a host system. An example system including a memory device and a processing device, operatively coupled with the memory device, to perform operations including: receiving a request of a host system to access a data block in the memory device; transmitting a response to the host system that indicates the data block is stored in a first buffer in host memory; determining the data block is related to a set of one or more data blocks stored at the memory device; and storing the set of one or more data blocks in a second buffer in the host memory, wherein the first buffer is controlled by the host system and the second buffer is controlled by a memory sub-system.
    Type: Grant
    Filed: December 21, 2021
    Date of Patent: November 14, 2023
    Assignee: Micron Technology, Inc
    Inventors: Muthazhagan Balasubramani, Venkatesh Anandpadmanabhan
  • LATENCY REDUCTION USING STREAM CACHE
    Publication number: 20230195635
    Abstract: A system and method for a memory sub-system to reduce latency by prefetching data blocks and preloading them into host memory of a host system. An example system including a memory device and a processing device, operatively coupled with the memory device, to perform operations including: receiving a request of a host system to access a data block in the memory device; transmitting a response to the host system that indicates the data block is stored in a first buffer in host memory; determining the data block is related to a set of one or more data blocks stored at the memory device; and storing the set of one or more data blocks in a second buffer in the host memory, wherein the first buffer is controlled by the host system and the second buffer is controlled by a memory sub-system.
    Type: Application
    Filed: December 21, 2021
    Publication date: June 22, 2023
    Inventors: Muthazhagan BALASUBRAMANI, Venkatesh ANANDPADMANABHAN