Abstract: The invention disclosed relates to a water-soluble composition having enhanced bioavailability useful for the treatment of depression which comprises a synergistic combination of curcumin, at least an antioxidant, a hydrophilic carrier and a fat. The invention also discloses a process for the preparation of the curcumin composition which comprises the steps of dissolving curcumin, at least one antioxidant, a hydrophilic carrier and a fat in a solvent to form a homogenous mass; warming the resultant mass at a temperature ranging from 25° C. to 60° C. for a period of 4 to 8 hours to obtain a dry wet mass; removing the solvent by evaporation to form dry mass and pulverizing the dry mass to form a fine powder.

Abstract: Hardware-based methods and apparatus are provided for training high speed data links used in data transfer applications. A data valid window is calibrated on one or more high speed links by determining an offset delay value for at least one datapath using a finite state machine, wherein the offset delay value is based on a maximum offset delay value and a minimum offset delay value for the at least one datapath; and delaying a read data strobe signal based upon a base delay and the offset delay value for the at least one datapath. The offset delay value can be, for example, an average of the maximum offset delay and the minimum offset delay. The received pattern can be a predefined pattern or a programmable pattern. In addition, the received pattern can cover single-bit transitions and/or multi-bit transitions.

Abstract: The invention disclosed relates to a water-soluble composition having enhanced bioavailability useful for the treatment of depression which comprises a synergistic combination of curcumin, at least an antioxidant, a hydrophilic carrier and a fat. The invention also discloses a process for the preparation of the curcumin composition which comprises the steps of dissolving curcumin, at least one antioxidant, a hydrophilic carrier and a fat in a solvent to form a homogenous mass; warming the resultant mass at a temperature ranging from 25° C. to 60° C. for a period of 4 to 8 hours to obtain a dry wet mass; removing the solvent by evaporation to form dry mass and pulverizing the dry mass to form a fine powder.

Abstract: Hardware-based methods and apparatus are provided for training high speed data links used in data transfer applications. A data valid window is calibrated on one or more high speed links by determining an offset delay value for at least one datapath using a finite state machine, wherein the offset delay value is based on a maximum offset delay value and a minimum offset delay value for the at least one datapath; and delaying a read data strobe signal based upon a base delay and the offset delay value for the at least one datapath. The offset delay value can be, for example, an average of the maximum offset delay and the minimum offset delay. The received pattern can be a predefined pattern or a programmable pattern. In addition, the received pattern can cover single-bit transitions and/or multi-bit transitions.

Abstract: The present invention is a method for providing address decode and Virtual Function (VF) migration support in a Peripheral Component Interconnect Express (PCIE) multi-root Input/Output Virtualization (IOV) environment. The method may include receiving a Transaction Layer Packet (TLP) from the PCIE multi-root IOV environment. The method may further include comparing a destination address of the TLP with a plurality of base address values stored in a Content Addressable Memory (CAM), each base address value being associated with a Virtual Function (VF), each VF being associated with a Physical Function (PF). The method may further include when a base address value included in the plurality of base address values matches the destination address of the TLP, providing the matching base address value to the PCIE multi-root IOV environment by outputting from the CAM the matching base address value.

Abstract: The present invention is a method for providing address decode and Virtual Function (VF) migration support in a Peripheral Component Interconnect Express (PCIE) multi-root Input/Output Virtualization (IOV) environment. The method may include receiving a Transaction Layer Packet (TLP) from the PCIE multi-root IOV environment. The method may further include comparing a destination address of the TLP with a plurality of base address values stored in a Content Addressable Memory (CAM), each base address value being associated with a Virtual Function (VF), each VF being associated with a Physical Function (PF). The method may further include when a base address value included in the plurality of base address values matches the destination address of the TLP, providing the matching base address value to the PCIE multi-root IOV environment by outputting from the CAM the matching base address value.

Abstract: The present invention is a method for providing address decode and Virtual Function (VF) migration support in a Peripheral Component Interconnect Express (PCIE) multi-root Input/Output Virtualization (IOV) environment. The method may include receiving a Transaction Layer Packet (TLP) from the PCIE multi-root IOV environment. The method may further include comparing a destination address of the TLP with a plurality of base address values stored in a Content Addressable Memory (CAM), each base address value being associated with a Virtual Function (VF), each VF being associated with a Physical Function (PF). The method may further include when a base address value included in the plurality of base address values matches the destination address of the TLP, providing the matching base address value to the PCIE multi-root IOV environment by outputting from the CAM the matching base address value.

Abstract: The link layer of the multi-root PCI (peripheral component interconnect) express device stores transaction layer packets (TLPs) sent from a transaction layer in a dedicated retry buffer dedicated to the virtual hierarchy (VH) associated with the TLP. The link layer of the multi-root device also stores information related to the TLP about the VH and an address of the TLP stored in the dedicated retry buffer in a sequence buffer. Upon receipt of a reset request for a VH, the link layer may purge the dedicated retry buffer associated with the VH. After purging, the multi-root device may send an ACK (acknowledge code) DLLP (data link layer packet), indicating that the VH has been successfully reset. By utilizing multiple retry buffers, the ACK DLLP response for a VH reset is sent as soon as the retry buffer pointers are reset to initial values.

Abstract: The present invention is a method for providing address decode and Virtual Function (VF) migration support in a Peripheral Component Interconnect Express (PCIE) multi-root Input/Output Virtualization (IOV) environment. The method may include receiving a Transaction Layer Packet (TLP) from the PCIE multi-root IOV environment. The method may further include comparing a destination address of the TLP with a plurality of base address values stored in a Content Addressable Memory (CAM), each base address value being associated with a Virtual Function (VF), each VF being associated with a Physical Function (PF). The method may further include when a base address value included in the plurality of base address values matches the destination address of the TLP, providing the matching base address value to the PCIE multi-root IOV environment by outputting from the CAM the matching base address value.

Abstract: The link layer of the multi-root PCI (peripheral component interconnect) express device stores transaction layer packets (TLPs) sent from a transaction layer in a dedicated retry buffer dedicated to the virtual hierarchy (VH) associated with the TLP. The link layer of the multi-root device also stores information related to the TLP about the VH and an address of the TLP stored in the dedicated retry buffer in a sequence buffer. Upon receipt of a reset request for a VH, the link layer may purge the dedicated retry buffer associated with the VH. After purging, the multi-root device may send an ACK (acknowledge code) DLLP (data link layer packet), indicating that the VH has been successfully reset. By utilizing multiple retry buffers, the ACK DLLP response for a VH reset is sent as soon as the retry buffer pointers are reset to initial values.

Abstract: A synthetic bulk laxative which comprises a crosslinked graft polymer. It is formed of a hydrophilic monomer partially neutralized up to 75%, a polysaccharide gum up to 3% by weight and a crosslinker up to 2% by weight. The weight percentages are with respect to the hydrophilic monomer. A process for the preparation of the synthetic bulk laxative which comprises up to 75% partial neutralization of a hydrophilic monomer with an alkali. The partially neutralized hydrophilic monomer is polymerized with up to 2% by weight of a cross linker and up to 3% by weight of a polysaccharide gum in the presence of an initiator in an organic solvent under inert atmosphere at 30–80° C. The synthetic bulk laxative is dried at 30–120° C. and pulverized. A formulation of the synthetic bulk laxative in combination with pharmaceutically acceptable excipients.

Abstract: Enteric coated stable oral pharmaceutical composition of acid unstable drug. The enteric coating is a bilayer with a pH gradient across its thickness comprising an inner layer of neutral or near neutral pH 7-7.5 and an outer layer of acidic pH 2-6. Also process for preparng the enteric coated stable oral pharmaceutical composition of acid unstable drug. The enteric coating is first carried out at neutral or near neutral pH of 7-7.5 to form an inner layer of neutral or near neutral pH and then at acidic pH of 2-6 to form an outer layer of acidic pH.