Patents by Inventor Venkatesh Gopinath
Venkatesh Gopinath has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240023345Abstract: Structures that include resistive memory elements and methods of forming a structure that includes resistive memory elements. The structure comprises a first plurality of resistive memory elements including a first plurality of bottom electrodes, a first top electrode, and a first switching layer between the first top electrode and the first plurality of bottom electrodes. The structure further comprises a second plurality of resistive memory elements including a second plurality of bottom electrodes, a second top electrode, and a second switching layer between the second top electrode and the second plurality of bottom electrodes. The first top electrode is shared by the first plurality of resistive memory elements, and the second top electrode is shared by the second plurality of resistive memory elements.Type: ApplicationFiled: July 18, 2022Publication date: January 18, 2024Inventors: Venkatesh Gopinath, Bipul C. Paul, Xiaoli Hu
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Patent number: 9524777Abstract: A method of controlling a resistive switching memory cell can include: receiving a first command to be executed on the resistive switching memory cell; performing, in response to the first command, an erase operation to erase the resistive switching memory cell to an erased state; verifying the erased state of the resistive switching memory cell; performing a weak program operation to program the resistive switching memory cell to a first programmed state; and verifying the first programmed state of the resistive switching memory cell.Type: GrantFiled: March 16, 2016Date of Patent: December 20, 2016Assignee: Adesto Technologies CorporationInventors: Deepak Kamalanathan, Ming Kwan, Venkatesh Gopinath, John Jameson
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Patent number: 8941089Abstract: In accordance with an embodiment of the present invention, a resistive switching device includes an opening disposed within a first dielectric layer, a conductive barrier layer disposed on sidewalls of the opening, a fill material including an inert material filling the opening. A solid electrolyte layer is disposed over the opening. The solid electrolyte contacts the fill material but not the conductive barrier layer. A top electrode is disposed over the solid electrolyte.Type: GrantFiled: February 14, 2013Date of Patent: January 27, 2015Assignee: Adesto Technologies CorporationInventors: Chakravarthy Gopalan, Jeffrey Shields, Venkatesh Gopinath, Janet Siao-Yian Wang, Kuei-Chang Tsai
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Patent number: 7413996Abstract: A method of forming a high k gate insulation layer in an integrated circuit on a substrate. A high k layer is deposited onto the substrate, and patterned with a mask to define the high k gate insulation layer and exposed portions of the high k layer. The exposed portions of the high k layer are subjected to an ion implanted species that causes lattice damage to the exposed portions of the high k layer. The lattice damaged exposed portions of the high k layer are etched to leave the high k gate insulation layer.Type: GrantFiled: April 14, 2003Date of Patent: August 19, 2008Assignee: LSI CorporationInventors: Arvind Kamath, Wai Lo, Venkatesh Gopinath
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Patent number: 6989331Abstract: A method of removing a hard mask layer from a patterned layer formed over an underlying layer, where the hard mask layer is removed using an etchant that detrimentally etches the underlying layer when the underlying layer is exposed to the etchant for a length of time typically required to remove the hard mask layer, without detrimentally etching the underlying layer. The hard mask layer is modified so that the hard mask layer is etched by the etchant at a substantially faster rate than that at which the etchant etches the underlying layer. The hard mask layer is patterned. The patterned layer is etched to expose portions of the underlying layer. Both the hard mask layer and the exposed portions of the underlying layer are etched with the etchant, where the etchant etches the hard mask layer at a substantially faster rate than that at which the etchant etches the underlying layer, because of the modification of the hard mask layer.Type: GrantFiled: July 8, 2003Date of Patent: January 24, 2006Assignee: LSI Logic CorporationInventors: Venkatesh Gopinath, Arvind Kamath, Mohammad R. Mirabedini, Ming-Yi Lee, Brian A. Baylis
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Publication number: 20050006347Abstract: A method of removing a hard mask layer from a patterned layer formed over an underlying layer, where the hard mask layer is removed using an etchant that detrimentally etches the underlying layer when the underlying layer is exposed to the etchant for a length of time typically required to remove the hard mask layer, without detrimentally etching the underlying layer. The hard mask layer is modified so that the hard mask layer is etched by the etchant at a substantially faster rate than that at which the etchant etches the underlying layer. The hard mask layer is patterned. The patterned layer is etched to expose portions of the underlying layer. Both the hard mask layer and the exposed portions of the underlying layer are etched with the etchant, where the etchant etches the hard mask layer at a substantially faster rate than that at which the etchant etches the underlying layer, because of the modification of the hard mask layer.Type: ApplicationFiled: July 8, 2003Publication date: January 13, 2005Inventors: Venkatesh Gopinath, Arvind Kamath, Mohammad Mirabedini, Ming-Yi Lee, Brian Baylis
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Patent number: 6812158Abstract: Growth of multiple gate oxides. By implanting different sites of a wafer with different doses of an oxide growth retardant, the entire wafer can grow oxides of different thicknesses even after being exposed to the same oxidation environment. The process is modular insofar as the implantation of one site has no effect on rate of growth of other sites.Type: GrantFiled: December 31, 2002Date of Patent: November 2, 2004Assignee: LSI Logic CorporationInventors: Wen-Chin Yeh, Venkatesh Gopinath, Arvind Kamath
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Publication number: 20040203246Abstract: A method of forming a high k gate insulation layer in an integrated circuit on a substrate. A high k layer is deposited onto the substrate, and patterned with a mask to define the high k gate insulation layer and exposed portions of the high k layer. The exposed portions of the high k layer are subjected to an ion implanted species that causes lattice damage to the exposed portions of the high k layer. The lattice damaged exposed portions of the high k layer are etched to leave the high k gate insulation layer.Type: ApplicationFiled: April 14, 2003Publication date: October 14, 2004Inventors: Arvind Kamath, Wai Lo, Venkatesh Gopinath
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Patent number: 6544829Abstract: A method of fabricating a substantially completely silicided polysilicon gate electrode in a CMOS process flow. A hard mask material is formed on an integrated circuit substrate, where the integrated circuit substrate includes an unpatterned polysilicon layer that overlies a gate oxide layer, and a well region disposed between isolation structures. Portions of the hard mask material are removed to define gate electrode masks that overlie first portions of the unpatterned polysilicon layer and the gate oxide layer, leaving exposed second portions of the unpatterned polysilicon layer and the gate oxide layer. The integrated circuit substrate is exposed to a dopant that passes through the second portions of the gate oxide layer but does not penetrate the first portions of the gate oxide layer that underlie the gate electrode masks, which defines source drain regions in the well region.Type: GrantFiled: September 20, 2002Date of Patent: April 8, 2003Assignee: LSI Logic CorporationInventors: Venkatesh Gopinath, Mohammad Mirabedini, Charles E. May, Arvind Kamath