Abstract: The automated changeover of a transfer encryption key from one transfer encryption key to another. This occurs in an environment in which a set of computing systems are to share one or more keys (such as a private and public key pair). The transfer encryption key is used to encrypt communications of the key(s) such that the encrypted key(s) may be transferred over a transfer system without the transfer system having access to the key(s). In order to perform automated changeover of the transfer encryption key, one of the set of computing systems encrypts the next transfer encryption key with the prior transfer encryption key. The transfer system provides this encrypted message to the remainder of the set of computing systems, which may then decrypt the encrypted message using the prior transfer encryption key, to find the next transfer encryption key.

Abstract: An architecture disposed in an integrated circuit for in-application programming of flash-based programmable logic devices includes a processor coupled to a processor system bus. An I/O peripheral is coupled to the processor over the system bus and is also coupled to an off-chip data source. A programmable logic device fabric includes flash-based programmable devices. A program controller is coupled to the flash-based programmable devices. An in-application programming controller is coupled to the program controller and is coupled to the processor over the system bus.

Abstract: The automated changeover of a transfer encryption key from one transfer encryption key to another. This occurs in an environment in which a set of computing systems are to share one or more keys (such as a private and public key pair). The transfer encryption key is used to encrypt communications of the key(s) such that the encrypted key(s) may be transferred over a transfer system without the transfer system having access to the key(s). In order to perform automated changeover of the transfer encryption key, one of the set of computing systems encrypts the next transfer encryption key with the prior transfer encryption key. The transfer system provides this encrypted message to the remainder of the set of computing systems, which may then decrypt the encrypted message using the prior transfer encryption key, to find the next transfer encryption key.

Abstract: Disclosed herein are systems, methods, and software for facilitating hybrid application environments. In at least one implementation, an application server within a hosting environment receives a data request initiated by a hosted application within the hosting environment. The hosted application may initiate the data request in response to a page request made on behalf of a hosted identity logged into the hosting environment. The application server generates a hybrid data request based on request information comprising at least a portion of the data request and the hosted identity and directs the hybrid data request over a connection established between the hosting environment and an enterprise environment for handling by an application server within the enterprise environment.

Abstract: An architecture disposed in an integrated circuit for in-application programming of flash-based programmable logic devices includes a processor coupled to a processor system bus. An I/O peripheral is coupled to the processor over the system bus and is also coupled to an off-chip data source. A programmable logic device fabric includes flash-based programmable devices. A program controller is coupled to the flash-based programmable devices. An in-application programming controller is coupled to the program controller and is coupled to the processor over the system bus.

Abstract: An architecture disposed in an integrated circuit for in-application programming of flash-based programmable logic devices includes a processor coupled to a processor system bus. An I/O peripheral is coupled to the processor over the system bus and is also coupled to an off-chip data source. A programmable logic device fabric includes flash-based programmable devices. A program controller is coupled to the flash-based programmable devices. An in-application programming controller is coupled to the program controller and is coupled to the processor over the system bus.

Abstract: Provided herein are systems, methods, and software for facilitating hybrid application environments. In at least one implementation, an application server within a hosting environment receives a data request initiated by a hosted application within the hosting environment. The hosted application may initiate the data request in response to a page request made on behalf of a hosted identity logged into the hosting environment. The application server generates a hybrid data request based on request information comprising at least a portion of the data request and the hosted identity and directs the hybrid data request over a connection established between the hosting environment and an enterprise environment for handling by an application server within the enterprise environment.

Abstract: An architecture disposed in an integrated circuit for in-application programming of flash-based programmable logic devices includes a processor coupled to a processor system bus. An I/O peripheral is coupled to the processor over the system bus and is also coupled to an off-chip data source. A programmable logic device fabric includes flash-based programmable devices. A program controller is coupled to the flash-based programmable devices. An in-application programming controller is coupled to the program controller and is coupled to the processor over the system bus.

Abstract: A programmable system-on-a-chip integrated circuit device comprises a programmable logic block, a non-volatile memory block, an analog sub-system, an analog input/output circuit block, and a digital input/output circuit block. A programmable interconnect architecture includes programmable elements and interconnect conductors. Ones of the programmable elements are coupled to the programmable logic block, the non-volatile memory block, the analog sub-system, the analog input/output circuit block, the digital input/output circuit block, and to the interconnect conductors, such that inputs and outputs of the programmable logic block, the non-volatile memory block, the analog sub-system, the analog input/output circuit block, and the digital input/output circuit block can be programmably coupled to one another.

Abstract: Described herein are one or more implementations for a mesh, peer-to-peer, cluster-tree, hierarchical wireless personal area network (WPAN) technology that uses a new approach to the static network address allocation scheme. As described herein, the new approach employs dynamic redemption or reallocation of free addresses from existing static allocations to other router-nodes in a WPAN.

Abstract: A method according to one embodiment may include receiving one or more packets from at least one external device and storing one or more packets in at least one queue in memory, the memory includes a plurality of queues and a plurality of queue descriptors having pointer information to point to a queue. The method may also include grouping a plurality of queues to form a group of queues; generating a group tag that associates the group of queues; storing said group tag in a register in a content addressable memory (CAM); and mapping the queue descriptors for each queue in the group of queues into a queue array, the group tag may point to more than one of the queue descriptors in the queue array. Of course, many alternatives, variations, and modifications are possible without departing from this embodiment.

Abstract: Embodiments of guaranteed timeslot usage management in wireless networks are described.

Abstract: A programmable system-on-a-chip integrated circuit device comprises a programmable logic block, a non-volatile memory block, an analog sub-system, an analog input/output circuit block, and a digital input/output circuit block. A programmable interconnect architecture includes programmable elements and interconnect conductors. Ones of the programmable elements are coupled to the programmable logic block, the non-volatile memory block, the analog sub-system, the analog input/output circuit block, the digital input/output circuit block, and to the interconnect conductors, such that inputs and outputs of the programmable logic block, the non-volatile memory block, the analog sub-system, the analog input/output circuit block, and the digital input/output circuit block can be programmably coupled to one another.

Abstract: A programmable system-on-a-chip integrated circuit device comprises a programmable logic block, a non-volatile memory block, an analog sub-system, an analog input/output circuit block, and a digital input/output circuit block. A programmable interconnect architecture includes programmable elements and interconnect conductors. Ones of the programmable elements are coupled to the programmable logic block, the non-volatile memory block, the analog sub-system, the analog input/output circuit block, the digital input/output circuit block, and to the interconnect conductors, such that inputs and outputs of the programmable logic block, the non-volatile memory block, the analog sub-system, the analog input/output circuit block, and the digital input/output circuit block can be programmably coupled to one another.

Abstract: A programmable system-on-a-chip integrated circuit device comprises a programmable logic block, a non-volatile memory block, an analog sub-system, an analog input/output circuit block, and a digital input/output circuit block. A programmable interconnect architecture includes programmable elements and interconnect conductors. Ones of the programmable elements are coupled to the programmable logic block, the non-volatile memory block, the analog sub-system, the analog input/output circuit block, the digital input/output circuit block, and to the interconnect conductors, such that inputs and outputs of the programmable logic block, the non-volatile memory block, the analog sub-system, the analog input/output circuit block, and the digital input/output circuit block can be programmably coupled to one another.

Abstract: A routing architecture in a field programmable gate array (FPGA) having a plurality of logic clusters wherein each logic cluster has at least two sub-clusters. The logic clusters are arranged in rows and columns and each logic clusters has a plurality of receiver components, a plurality of transmitter components, at least one buffer module, at least one sequential logic component and at least one combinatorial logic component. A first-level routing architecture is programmably coupled to the logic clusters and a second-level routing architecture is programmably coupled to the logic clusters and to the first-level routing architecture through at least one of the transmitter components and at least one of the receiver components.

Abstract: Described herein are one or more implementations for a mesh, peer-to-peer, cluster-tree, hierarchical wireless personal area network (WPAN) technology that uses a new approach to the static network address allocation scheme. As described herein, the new approach employs dynamic redemption or reallocation of free addresses from existing static allocations to other router-nodes in a WPAN.

Abstract: A programmable system-on-a-chip integrated circuit device comprises a programmable logic block, a non-volatile memory block, an analog sub-system, an analog input/output circuit block, and a digital input/output circuit block. A programmable interconnect architecture includes programmable elements and interconnect conductors. Ones of the programmable elements are coupled to the programmable logic block, the non-volatile memory block, the analog sub-system, the analog input/output circuit block, the digital input/output circuit block, and to the interconnect conductors, such that inputs and outputs of the programmable logic block, the non-volatile memory block, the analog sub-system, the analog input/output circuit block, and the digital input/output circuit block can be programmably coupled to one another.

Abstract: Embodiments of guaranteed timeslot usage management in wireless networks are described.

Abstract: A programmable system-on-a-chip integrated circuit device comprises a programmable logic block, a non-volatile memory block, an analog sub-system, an analog input/output circuit block, and a digital input/output circuit block. A programmable interconnect architecture includes programmable elements and interconnect conductors. Ones of the programmable elements are coupled to the programmable logic block, the non-volatile memory block, the analog sub-system, the analog input/output circuit block, the digital input/output circuit block, and to the interconnect conductors, such that inputs and outputs of the programmable logic block, the non-volatile memory block, the analog sub-system, the analog input/output circuit block, and the digital input/output circuit block can be programmably coupled to one another.