Patents by Inventor Venkatesh P. Gopinth

Venkatesh P. Gopinth has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method of shallow trench isolation formation and planarization
    Patent number: 6949446
    Abstract: Provided is a technique for fabrication of STIs in a semiconductor device using implantation of damaging high-energy ions to insulating material overburden to generally and/or selectively increase insulation overburden removal rates. This technique avoids the use of chemical mechanical planarization (CMP) with a combination of implantation and, in some instances, low cost batch etching. The electrical characteristics of devices created with the new technique match closely to those fabricated with the standard CMP-based technique.
    Type: Grant
    Filed: June 9, 2003
    Date of Patent: September 27, 2005
    Assignee: LSI Logic Corporation
    Inventors: Arvind Kamath, Venkatesh P. Gopinth
  • Method of shallow trench isolation formation and planarization
    Patent number: 6617251
    Abstract: Provided is a technique for fabrication of STIs in a semiconductor device using implantation of damaging high-energy ions to insulating material overburden to generally and/or selectively increase insulation overburden removal rates. This technique avoids the use of chemical mechanical planarization (CMP) with a combination of implantation and, in some instances, low cost batch etching. The electrical characteristics of devices created with the new technique match closely to those fabricated with the standard CMP-based technique.
    Type: Grant
    Filed: June 19, 2001
    Date of Patent: September 9, 2003
    Assignee: LSI Logic Corporation
    Inventors: Arvind Kamath, Venkatesh P. Gopinth