Abstract: A device implementing a system to associate a user account with a content output device includes at least one processor configured to receive an invitation to access content associated with a first user account on another device associated with a second user account, the other device being connected to a local area network. The at least one processor is further configured to send, to a server, a request for authorization to access the content associated with the first user account on the other device associated with the second user account, the request comprising information included with the invitation, and to receive, from the server, the authorization to access the content. The at least one processor is further configured to access, based at least in part on the authorization, the content associated with the first user account on the other device associated with the second user account.

Abstract: Described are substrates including a layer of an aluminum alloy with a conductive coating, also referred to as a protective overlayer. The conductive coating can prevent certain material from coming into contact with the aluminum alloy layer while allowing transmission of electrons to the aluminum alloy. The substrates may be used, for example, in electronics applications, such as current collectors or electrodes for batteries, electrochemical cells, capacitors, supercapacitors, or the like.

Abstract: Disclosed is a metal foil capacitor, preferably an aluminum capacitor, comprising a modified metal foil comprising a base metal, preferably an aluminum foil. The modified metal foil capacitor may satisfy at least two of the following conditions: (a) the modified metal foil has a surface area of at least 10 times greater than an unmodified metal foil; (b) the modified metal foil has a dielectric constant (k) of at least 5; (c) the modified metal foil has a thickness of at least 1 micron; and/or (d) the modified metal foil comprises at least one metal in addition to the base metal, wherein the at least one metal is present in an amount of at least 0.01 wt. % based on the total weight of the modified metal foil. Methods for preparing the metal foil capacitor are also disclosed.

Abstract: Multi-terminal capacitor devices and methods of making multi-terminal capacitor devices are described herein. The multi-terminal capacitor devices may include a plurality of individual capacitors arranged in a single device layer, such as high surface area capacitors. A individual capacitor may include an aluminum foil-based electrode, an aluminum oxide dielectric layer conformal with the aluminum foil-based electrode, and a conductive material electrode, such as a conducting polymer or a conductive ceramic, in conformal contact with the dielectric layer.

Abstract: Disclosed herein are, for instance, methods for producing through package vias in a glass interposer. For instance, disclosed herein is a method for producing through package vias in a glass interposer comprising laminating a polymer on at least a portion of a top surface of a glass interposer, removing at least a portion of the polymer and the glass interposer to form a through via, filling at least a portion of the through via with a metal conductor to form a metallization layer, and selectively removing a portion of the metallization layer to form a metalized through package via. Other methods are also disclosed, along with through-package-via structures in glass interposers produced therefrom.

Abstract: Described herein are anodized continuous coils containing a thin anodized film layer and systems and methods for making and using the same. The anodized continuous coils include an aluminum alloy continuous coil, wherein a surface of the aluminum alloy continuous coil comprises a thin anodized film layer and a chemical additive layer. The thin anodized film layer can be a dielectric for electronic device applications.

Abstract: An optical interposer that includes a glass substrate having one or more optical vias extending through the glass substrate. A first optical polymer may be bonded to the substrate and to interior surfaces of the one or more optical vias. Implementations include one or more optical via cores comprising a second optical polymer that has a greater refractive index than the first optical polymer. The one or more optical via cores may be at least partially surrounded by the first optical polymer. Embodiments include encapsulated optical waveguides in communication with the optical vias and/or via cores. Example implementations include layers of electrical insulation, electrical traces, and electrical vias. A method of manufacture includes forming the optical vias by laser ablation. Certain embodiments may include chemically etching the inside of the vias to improve surface roughness.

Abstract: Disclosed herein are, for instance, methods for producing through package vias in a glass interposer. For instance, disclosed herein is a method for producing through package vias in a glass interposer comprising laminating a polymer on at least a portion of a top surface of a glass interposer, removing at least a portion of the polymer and the glass interposer to form a through via, filling at least a portion of the through via with a metal conductor to form a metallization layer, and selectively removing a portion of the metallization layer to form a metalized through package via. Other methods are also disclosed, along with through-package-via structures in glass interposers produced therefrom.

Abstract: A electromagnetic interference shielding device is disclosed having a first substrate one or more surfaces. One or more laminates are operatively attached to the one or more surfaces of the first substrate. A cavity is provided that is defined by the first substrate and its corresponding one or more laminates and at least one inner lateral portion. The cavity is operable to receive one or more microelectromechanical system (MEMS) components. A first conductive structure integrally formed with a trench or via array of the substrate spans a thickness defined by one or more of surfaces of the first substrate, the first conductive structure operable to shield electromagnetic interference between MEMS components assembled with the first substrate.

Abstract: Disclosed herein are edge-coated microelectronic packages comprising a microelectronic package having a top, a bottom, and an exposed edge, and a coating comprising a polymer, wherein the microelectronic package comprises a glass substrate, and wherein the coating covers at least a portion of the top, at least a portion of the bottom, and at least a portion of the exposed edge of the microelectronic package. Also disclosed herein are methods of making and using edge-coated microelectronic packages.

Abstract: An embodiment provides an optical interconnect comprising first and second planar metallization layers, a glass substrate disposed between at least portions of the first and second metallization layers, an aperture in the second metallization layer having a first and second ends, and a polymer waveguide having a first end adjacent the first end of the aperture. The first end of the waveguide can have a first edge defining a first acute angle with respect to a top surface of the waveguide. The first end of the optical waveguide can be configured to receive an optical signal traversing through the glass substrate from a source proximate a first position on a top surface of the glass substrate and direct the optical signal with the first edge in a direction parallel to the glass substrate towards a second end of the waveguide.

Abstract: Aspects of the present disclosure generally relate to a microelectronic package including a plurality of through vias having walls in a glass interposer having a top portion and a bottom portion. The microelectric package may also include a stress relief barrier on at least a portion of the top and bottom portions of the glass interposer. The microelectric package may further include a metallization seed layer on at least a portion of the stress relief layer and a conductor on at least a portion of the metallization seed layer. The conductor extends through at least a portion of the plurality of the through vias, forming a plurality of metalized through package vias. At least a portion of the through vias are filled with the stress relief layer or the metallization seed layer.

Abstract: The various embodiments of the present invention provide a stress-relieving, second-level interconnect structure that is low-cost and accommodates TCE mismatch between low-TCE packages and PCBs. The various embodiments of the interconnect structure are reworkable and can be scaled to pitches from about 1 millimeter (mm) to about 150 micrometers (?m). The interconnect structure comprises a dielectric body element and at least one interconnection array that provides a conductive path between two electronic components. Each interconnection array comprises a plurality of wires that provide both conductivity and compliance to the overall interconnect structure. The versatility and scalability of the interconnect structure of the present invention make it a desirable structure to utilize in current two-dimensional and ever-evolving three-dimensional IC structures.

Abstract: An optical interposer that includes a glass substrate having one or more optical vias extending through the glass substrate. A first optical polymer may be bonded to the substrate and to interior surfaces of the one or more optical vias. Implementations include one or more optical via cores comprising a second optical polymer that has a greater refractive index than the first optical polymer. The one or more optical via cores may be at least partially surrounded by the first optical polymer. Embodiments include encapsulated optical waveguides in communication with the optical vias and/or via cores. Example implementations include layers of electrical insulation, electrical traces, and electrical vias. A method of manufacture includes forming the optical vias by laser ablation. Certain embodiments may include chemically etching the inside of the vias to improve surface roughness.

Abstract: Exemplary embodiments provide a nanomagnetic structure and method of making the same, comprising a device substrate, a plurality of nanomagnetic composite layers disposed on the device substrate, wherein an adhesive layer is interposed between each of the plurality of nanomagnetic composite layers. Metal windings are integrated within the plurality of nanomagnetic composite layers to form an inductor core, wherein the nanomagnetic structure has a thickness ranging from about 5 to about 100 microns.

Abstract: The various embodiments of the present invention provide fine pitch, chip-to-substrate hybrid interconnect assemblies, as well as methods of making and using the assemblies. The hybrid assemblies generally include a semiconductor having a die pad disposed thereon, a substrate having a substrate pad disposed thereon, and a polymer layer disposed between the surface of the die pad and the surface of the substrate pad. In addition, at least a portion of the surface of the die pad is metallically bonded to at least a portion of the surface of the substrate pad and at least a portion of the surface of the die pad is chemically bonded to at least a portion of the surface of the substrate pad.

Abstract: The various embodiments of the present invention provide a novel chip-last embedded structure, wherein an IC is embedded within a one to two metal layer substrate. The various embodiments of the present invention are comparable to other two-dimensional and three-dimensional WLFO packages of the prior art as the embodiments have similar package thicknesses and X-Y form factors, short interconnect lengths, fine-pitch interconnects to chip I/Os, a reduced layer count for re-distribution of chip I/O pads to ball grid arrays (BGA) or land grid arrays (LGA), and improved thermal management options.

Abstract: The present invention generally relates to the use of glass as the interposer material with the surface of the interposer and/or the walls of through vias in being coated by a stress relief barrier that provides thermal expansion and contraction stress relief and better metallization capabilities. The present invention discloses ways in that a stress relief barrier can be used to reduce the effects of stress caused by the different CTEs while also, in some applications, acting as an adhesion promoter between the metallization and the interposer. The stress relief barrier acts to absorb some of the stress caused by the different CTEs and promotes better adhesion for the conductive metal layer, thus helping to increase reliability while also providing for smaller designs.

Abstract: The various embodiments of the present invention provide a stress-relieving, second-level interconnect structure that is low-cost and accommodates TCE mismatch between low-TCE packages and PCBs. The various embodiments of the interconnect structure are reworkable and can be scaled to pitches from about 1 millimeter (mm) to about 150 micrometers (?m). The interconnect structure comprises a dielectric body element and at least one interconnection array that provides a conductive path between two electronic components. Each interconnection array comprises a plurality of wires that provide both conductivity and compliance to the overall interconnect structure. The versatility and scalability of the interconnect structure of the present invention make it a desirable structure to utilize in current two-dimensional and ever-evolving three-dimensional IC structures.

Abstract: Provided are semiconductor packages comprising at least one thin-film capacitor attached to a printed wiring board core through build-up layers, wherein a first electrode of the thin-film capacitor comprises a thin nickel foil, a second electrode of the thin-film capacitor comprises a copper electrode, and a copper layer is formed on the nickel foil. The interconnections between the thin-film capacitor and the semiconductor device provide a low inductance path to transfer charge to and from the semiconductor device. Also provided are methods for fabricating such semiconductor packages.