Patents by Inventor Venkatesh Wadeyar

Venkatesh Wadeyar has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Architecture to mitigate overshoot/undershoot in a voltage regulator
    Patent number: 11955879
    Abstract: In described examples, a controller includes a converter. The converter generates a first signal responsive to an input signal. A summing block is coupled to the converter. The summing block receives the first signal and generates a second signal. A limiter is coupled to the summing block and generates a third signal responsive to the second signal and a code signal. A logic block generates a target signal responsive to the third signal. The third signal transitions to an intermediate level at a first slew rate and the third signal transitions from the intermediate level to the target signal at a second slew rate.
    Type: Grant
    Filed: December 30, 2020
    Date of Patent: April 9, 2024
    Assignee: Texas Instruments Incorporated
    Inventors: Venkatesh Wadeyar, Vikas Lakhanpal, Preetam Charan Anand Tadeparthy
  • SWITCHING CONVERTER CONTROL LOOP AND DYNAMIC REFERENCE VOLTAGE ADJUSTMENT
    Publication number: 20240113623
    Abstract: A controller includes: a pulse-width modulation (PWM) circuit; a control loop; and a reference voltage controller. The control loop has: a feedback input adapted to be coupled to an output voltage of a power stage; a control loop output coupled to a PWM control input; and an operational amplifier with a first feedback input, a first reference input, and an amplifier output, the first feedback input connected to the feedback input, and the amplifier output coupled to the PWM control input. The reference voltage controller has a reference voltage output coupled to the first reference input, the reference voltage controller configured to adjust a reference voltage provided to the reference voltage output responsive to a dynamic error estimate based on error in the operational amplifier.
    Type: Application
    Filed: December 14, 2023
    Publication date: April 4, 2024
    Inventors: Bikash Kumar PRADHAN, Preetam Charan Anand TADEPARTHY, Muthusubramanian VENKATESWARAN, Venkatesh WADEYAR, Siddaram MATHAPATHI
  • Switching converter control loop and dynamic reference voltage adjustment
    Patent number: 11881774
    Abstract: A controller includes: a pulse-width modulation (PWM) circuit; a control loop; and a reference voltage controller. The control loop has: a feedback input adapted to be coupled to an output voltage of a power stage; a control loop output coupled to a PWM control input; and an operational amplifier with a first feedback input, a first reference input, and an amplifier output, the first feedback input connected to the feedback input, and the amplifier output coupled to the PWM control input. The reference voltage controller has a reference voltage output coupled to the first reference input, the reference voltage controller configured to adjust a reference voltage provided to the reference voltage output responsive to a dynamic error estimate based on error in the operational amplifier.
    Type: Grant
    Filed: March 12, 2021
    Date of Patent: January 23, 2024
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Bikash Kumar Pradhan, Preetam Charan Anand Tadeparthy, Muthusubramanian Venkateswaran, Venkatesh Wadeyar, Siddaram Mathapathi
  • Unified bus architecture for a voltage regulator
    Patent number: 11720159
    Abstract: In described examples, a voltage regulator includes a processor. A register bank is coupled to the processor. A logic block is coupled to the processor and to the register bank. The logic block receives frames. The processor programs the logic block and the register bank based on at least one of the frames.
    Type: Grant
    Filed: June 30, 2020
    Date of Patent: August 8, 2023
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Venkatesh Wadeyar, Vikas Lakhanpal, Preetam Charan Anand Tadeparthy
  • SWITCHING CONVERTER CONTROL LOOP AND DYNAMIC REFERENCE VOLTAGE ADJUSTMENT
    Publication number: 20220294344
    Abstract: A controller includes: a pulse-width modulation (PWM) circuit; a control loop; and a reference voltage controller. The control loop has: a feedback input adapted to be coupled to an output voltage of a power stage; a control loop output coupled to a PWM control input; and an operational amplifier with a first feedback input, a first reference input, and an amplifier output, the first feedback input connected to the feedback input, and the amplifier output coupled to the PWM control input. The reference voltage controller has a reference voltage output coupled to the first reference input, the reference voltage controller configured to adjust a reference voltage provided to the reference voltage output responsive to a dynamic error estimate based on error in the operational amplifier.
    Type: Application
    Filed: March 12, 2021
    Publication date: September 15, 2022
    Inventors: Bikash Kumar PRADHAN, Preetam Charan Anand TADEPARTHY, Muthusubramanian VENKATESWARAN, Venkatesh WADEYAR, Siddaram MATHAPATHI
  • ARCHITECTURE TO MITIGATE OVERSHOOT/UNDERSHOOT IN A VOLTAGE REGULATOR
    Publication number: 20220209648
    Abstract: In described examples, a controller includes a converter. The converter generates a first signal responsive to an input signal. A summing block is coupled to the converter. The summing block receives the first signal and generates a second signal. A limiter is coupled to the summing block and generates a third signal responsive to the second signal and a code signal. A logic block generates a target signal responsive to the third signal. The third signal transitions to an intermediate level at a first slew rate and the third signal transitions from the intermediate level to the target signal at a second slew rate.
    Type: Application
    Filed: December 30, 2020
    Publication date: June 30, 2022
    Inventors: Venkatesh Wadeyar, Vikas Lakhanpal, Preetam Charan Anand Tadeparthy
  • UNIFIED BUS ARCHITECTURE FOR A VOLTAGE REGULATOR
    Publication number: 20210004072
    Abstract: In described examples, a voltage regulator includes a processor. A register bank is coupled to the processor. A logic block is coupled to the processor and to the register bank. The logic block receives frames. The processor programs the logic block and the register bank based on at least one of the frames.
    Type: Application
    Filed: June 30, 2020
    Publication date: January 7, 2021
    Inventors: Venkatesh Wadeyar, Vikas Lakhanpal, Preetam Charan Anand Tadeparthy