Patents by Inventor Venkateshwaran Vaiyapuri
Venkateshwaran Vaiyapuri has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7514776Abstract: A method of forming a computer system and a printed circuit board assembly, are provided comprising first and second semiconductor dies and an intermediate substrate. The intermediate substrate is positioned between the first active surface of the first semiconductor die and the second active surface of the second semiconductor die such that a first surface of the intermediate substrate faces the first active surface and such that a second surface of the intermediate substrate faces the second active surface. The second surface of the intermediate substrate includes a cavity defined therein. The intermediate substrate defines a passage there through. The second semiconductor die is secured to the second surface of the intermediate substrate within the cavity such that the conductive bond pad of the second semiconductor die is aligned with the passage.Type: GrantFiled: January 29, 2007Date of Patent: April 7, 2009Assignee: Micron Technology, Inc.Inventor: Venkateshwaran Vaiyapuri
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Patent number: 7427535Abstract: A method of forming a computer system and a printed circuit board assembly, are provided comprising first and second semiconductor dies and an intermediate substrate. The intermediate substrate is positioned between the first active surface of the first semiconductor die and the second active surface of the second semiconductor die such that a first surface of the intermediate substrate faces the first active surface and such that a second surface of the intermediate substrate faces the second active surface. The second surface of the intermediate substrate includes a cavity defined therein. The intermediate substrate defines a passage there through. The second semiconductor die is secured to the second surface of the intermediate substrate within the cavity such that the conductive bond pad of the second semiconductor die is aligned with the passage.Type: GrantFiled: December 16, 2004Date of Patent: September 23, 2008Assignee: Micron Technology, Inc.Inventor: Venkateshwaran Vaiyapuri
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Publication number: 20070120238Abstract: A method of forming a computer system and a printed circuit board assembly, are provided comprising first and second semiconductor dies and an intermediate substrate. The intermediate substrate is positioned between the first active surface of the first semiconductor die and the second active surface of the second semiconductor die such that a first surface of the intermediate substrate faces the first active surface and such that a second surface of the intermediate substrate faces the second active surface. The second surface of the intermediate substrate includes a cavity defined therein. The intermediate substrate defines a passage there through. The second semiconductor die is secured to the second surface of the intermediate substrate within the cavity such that the conductive bond pad of the second semiconductor die is aligned with the passage.Type: ApplicationFiled: January 29, 2007Publication date: May 31, 2007Applicant: MICRON TECHNOLOGY, INC.Inventor: Venkateshwaran Vaiyapuri
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Publication number: 20060236711Abstract: A cooling mechanism within an integrated circuit includes an internal pump for circulating thermally conductive fluid within closed loop channels. The cooling channels are embedded within an integrated circuit die, such as in interlevel dielectric layers between metal levels. The channels are formed by engineering deposition of a layer to line trenches and form continuous voids along the trenches. Exemplary heat pumps comprise cavities, formed in communication with the channels, covered by piezoelectric actuators. Preferably, the actuators are wired to act in sequence as a peristaltic pump, circulating the fluid within the channels. The channels are positioned to carry heat from active devices within the integrated circuit, and a heat sink carries heat from the die.Type: ApplicationFiled: June 20, 2006Publication date: October 26, 2006Inventors: Venkateshwaran Vaiyapuri, Fred Fishburn
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Publication number: 20060236710Abstract: A cooling mechanism within an integrated circuit includes an internal pump for circulating thermally conductive fluid within closed loop channels. The cooling channels are embedded within an integrated circuit die, such as in interlevel dielectric layers between metal levels. The channels are formed by engineering deposition of a layer to line trenches and form continuous voids along the trenches. Exemplary heat pumps comprise cavities, formed in communication with the channels, covered by piezoelectric actuators; Preferably, the actuators are wired to act in sequence as a peristaltic pump, circulating the fluid within the channels. The channels are positioned to carry heat from active devices within the integrated circuit, and a heat sink carries heat from the die.Type: ApplicationFiled: June 20, 2006Publication date: October 26, 2006Inventors: Venkateshwaran Vaiyapuri, Fred Fishburn
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Patent number: 7107777Abstract: A cooling mechanism within an integrated circuit includes an internal pump for circulating thermally conductive fluid within closed loop channels. The cooling channels are embedded within an integrated circuit die, such as in interlevel dielectric layers between metal levels. The channels are formed by engineering deposition of a layer to line trenches and form continuous voids along the trenches. Exemplary heat pumps comprise cavities, formed in communication with the channels, covered by piezoelectric actuators. Preferably, the actuators are wired to act in sequence as a peristaltic pump, circulating the fluid within the channels. The channels are positioned to carry heat from active devices within the integrated circuit, and a heat sink carries heat from the die.Type: GrantFiled: August 12, 2003Date of Patent: September 19, 2006Assignee: Micro Technology, Inc.Inventors: Venkateshwaran Vaiyapuri, Fred Fishburn
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Publication number: 20060189022Abstract: A cooling mechanism within an integrated circuit includes an internal pump for circulating thermally conductive fluid within closed loop channels. The cooling channels are embedded within an integrated circuit die, such as in interlevel dielectric layers between metal levels. The channels are formed by engineering deposition of a layer to line trenches and form continuous voids along the trenches. Exemplary heat pumps comprise cavities, formed in communication with the channels, covered by piezoelectric actuators. Preferably, the actuators are wired to act in sequence as a peristaltic pump, circulating the fluid within the channels. The channels are positioned to carry heat from active devices within the integrated circuit, and a heat sink carries heat from the die.Type: ApplicationFiled: April 24, 2006Publication date: August 24, 2006Inventors: Venkateshwaran Vaiyapuri, Fred Fishburn
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Patent number: 7084004Abstract: A cooling mechanism within an integrated circuit includes an internal pump for circulating thermally conductive fluid within closed loop channels. The cooling channels are embedded within an integrated circuit die, such as in interlevel dielectric layers between metal levels. The channels are formed by engineering deposition of a layer to line trenches and form continuous voids along the trenches. Exemplary heat pumps comprise cavities, formed in communication with the channels, covered by piezoelectric actuators. Preferably, the actuators are wired to act in sequence as a peristaltic pump, circulating the fluid within the channels. The channels are positioned to carry heat from active devices within the integrated circuit, and a heat sink carries heat from the die.Type: GrantFiled: August 12, 2003Date of Patent: August 1, 2006Assignee: Micron Technology, Inc.Inventors: Venkateshwaran Vaiyapuri, Fred Fishburn
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Publication number: 20050106780Abstract: A method of forming a computer system and a printed circuit board assembly, are provided comprising first and second semiconductor dies and an intermediate substrate. The intermediate substrate is positioned between the first active surface of the first semiconductor die and the second active surface of the second semiconductor die such that a first surface of the intermediate substrate faces the first active surface and such that a second surface of the intermediate substrate faces the second active surface. The second surface of the intermediate substrate includes a cavity defined therein. The intermediate substrate defines a passage there through. The second semiconductor die is secured to the second surface of the intermediate substrate within the cavity such that the conductive bond pad of the second semiconductor die is aligned with the passage.Type: ApplicationFiled: December 16, 2004Publication date: May 19, 2005Inventor: Venkateshwaran Vaiyapuri
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Patent number: 6869827Abstract: A method of forming a computer system and a printed circuit board assembly, are provided comprising first and second semiconductor dies and an intermediate substrate. The intermediate substrate is positioned between the first active surface of the first semiconductor die and the second active surface of the second semiconductor die such that a first surface of the intermediate substrate faces the first active surface and such that a second surface of the intermediate substrate faces the second active surface. The second surface of the intermediate substrate includes a cavity defined therein. The intermediate substrate defines a passage there through. The second semiconductor die is secured to the second surface of the intermediate substrate within the cavity such that the conductive bond pad of the second semiconductor die is aligned with the passage.Type: GrantFiled: August 28, 2002Date of Patent: March 22, 2005Assignee: Micron Technology, Inc.Inventor: Venkateshwaran Vaiyapuri
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Patent number: 6844217Abstract: Disclosed is a method of forming a support structure for supporting multiple dies and resulting structure. The support structure has a cavity with an upper die support surface, sidewalls providing the upper die support surface, and a lower die support bottom surface connected with the sidewalls. The support structure can be formed of a plurality of layers. A first semiconductor die is secured on the lower die support surface and a second semiconductor die is secured to the upper die support surface. An aperture can be formed from the structure bottom surface to the cavity to facilitate electrical connections between the first die and electrical contact areas on the support structure. An encapsulating material is formed around the dies, the electrical connections, and the vacant cavity space to form a packaged semiconductor device.Type: GrantFiled: October 10, 2001Date of Patent: January 18, 2005Assignee: Micron Technology, Inc.Inventor: Venkateshwaran Vaiyapuri
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Patent number: 6798055Abstract: Disclosed is a method of forming a support structure for supporting multiple dice and resulting structure. The support structure has a cavity with an upper die support surface, sidewalls providing the upper die support surface, and a lower die support bottom surface connected with the sidewalls. The support structure can be formed of a plurality of layers. A first semiconductor die is secured on the lower die support surface and a second semiconductor die is secured to the upper die support surface. An aperture can be formed from the structure bottom surface to the cavity to facilitate electrical connections between the first die and electrical contact areas on the support structure. An encapsulating material is formed around the dice, the electrical connections, and the vacant cavity space to form a packaged semiconductor device.Type: GrantFiled: June 20, 2002Date of Patent: September 28, 2004Assignee: Micron TechnologyInventor: Venkateshwaran Vaiyapuri
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Methods for fabricating dual loc semiconductor die assembly employing floating lead finger structure
Patent number: 6762079Abstract: A method and apparatus for increasing integrated circuit density in a semiconductor die assembly, and specifically, a dual LOC semiconductor die assembly. A first and a second die are substantially symmetrically back bonded to a die attach site on opposing sides of a base lead frame. A first and a second offset lead frame, each having a plurality of lead fingers, are then attached to the base lead frame on opposing sides thereof so that their lead fingers respectively extend over the first and second dice in a cantilevered manner. Wire bonds are formed between lead ends of each of the lead fingers to corresponding bond pads on the first and second dice for electrical connection therebetween. The assembly is then encapsulated in a transfer molding process, after which the stacked dual LOC semiconductor assembly is subjected to a trim and form operation.Type: GrantFiled: February 25, 2002Date of Patent: July 13, 2004Assignee: Micron Technology, Inc.Inventor: Venkateshwaran Vaiyapuri -
Publication number: 20040031281Abstract: A cooling mechanism within an integrated circuit includes an internal pump for circulating thermally conductive fluid within closed loop channels. The cooling channels are embedded within an integrated circuit die, such as in interlevel dielectric layers between metal levels. The channels are formed by engineering deposition of a layer to line trenches and form continuous voids along the trenches. Exemplary heat pumps comprise cavities, formed in communication with the channels, covered by piezoelectric actuators. Preferably, the actuators are wired to act in sequence as a peristaltic pump, circulating the fluid within the channels. The channels are positioned to carry heat from active devices within the integrated circuit, and a heat sink carries heat from the die.Type: ApplicationFiled: August 12, 2003Publication date: February 19, 2004Inventors: Venkateshwaran Vaiyapuri, Fred Fishburn
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Publication number: 20040031594Abstract: A cooling mechanism within an integrated circuit includes an internal pump for circulating thermally conductive fluid within closed loop channels. The cooling channels are embedded within an integrated circuit die, such as in interlevel dielectric layers between metal levels. The channels are formed by engineering deposition of a layer to line trenches and form continuous voids along the trenches. Exemplary heat pumps comprise cavities, formed in communication with the channels, covered by piezoelectric actuators. Preferably, the actuators are wired to act in sequence as a peristaltic pump, circulating the fluid within the channels. The channels are positioned to carry heat from active devices within the integrated circuit, and a heat sink carries heat from the die.Type: ApplicationFiled: August 12, 2003Publication date: February 19, 2004Inventors: Venkateshwaran Vaiyapuri, Fred Fishburn
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Patent number: 6629425Abstract: A cooling mechanism within an integrated circuit includes an internal pump for circulating thermally conductive fluid within closed loop channels. The cooling channels are embedded within an integrated circuit die, such as in interlevel dielectric layers between metal levels. The channels are formed by engineering deposition of a layer to line trenches and form continuous voids along the trenches. Exemplary heat pumps comprise cavities, formed in communication with the channels, covered by piezoelectric actuators. Preferably, the actuators are wired to act in sequence as a peristaltic pump, circulating the fluid within the channels. The channels are positioned to carry heat from active devices within the integrated circuit, and a heat sink carries heat from the die.Type: GrantFiled: July 23, 2001Date of Patent: October 7, 2003Assignee: Micron Technology, Inc.Inventor: Venkateshwaran Vaiyapuri
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Patent number: 6541846Abstract: A method and apparatus for increasing integrated circuit density in a semiconductor die assembly, and specifically, a dual LOC semiconductor die assembly. A first and a second die are substantially symmetrically back bonded to a die attach site on a opposing sides of a base lead frame. A first and a second offset lead frame, each having a plurality of lead fingers, are then attached to the base lead frame on opposing sides thereof so that their lead fingers respectively extend over the first and second dice in a cantilevered manner. Wire bonds are formed between lead ends of each of the lead fingers to corresponding bond pads on the first and second dice for electrical connection therebetween. The assembly is then encapsulated in a transfer molding process, after which the stacked dual LOC semiconductor assembly is subjected to a trim and form operation.Type: GrantFiled: January 23, 2001Date of Patent: April 1, 2003Assignee: Micron Technology, Inc.Inventor: Venkateshwaran Vaiyapuri
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Patent number: 6507107Abstract: A computer system and a printed circuit board assembly are provided comprising first and second semiconductor dies and an intermediate substrate. The intermediate substrate is positioned between a first active surface of the first semiconductor die and a second active surface of the second semiconductor die. The first semiconductor die is electrically coupled to the intermediate substrate. The intermediate substrate defines a passage there through The second semiconductor die is secured to the second surface of the intermediate substrate within a cavity in the second surface of the intermediate substrate such that the conductive bond pad of the second semiconductor die is aligned with the passage. The second semiconductor die is electrically coupled to the intermediate substrate by at least one conductive line extending from the second semiconductor die through the passage and to the first surface of the intermediate substrate.Type: GrantFiled: May 15, 2001Date of Patent: January 14, 2003Assignee: Micron Technology, Inc.Inventor: Venkateshwaran Vaiyapuri
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Publication number: 20030006496Abstract: A method of forming a computer system and a printed circuit board assembly, are provided comprising first and second semiconductor dies and an intermediate substrate. The intermediate substrate is positioned between the first active surface of the first semiconductor die and the second active surface of the second semiconductor die such that a first surface of the intermediate substrate faces the first active surface and such that a second surface of the intermediate substrate faces the second active surface. The second surface of the intermediate substrate includes a cavity defined therein. The intermediate substrate defines a passage there through. The second semiconductor die is secured to the second surface of the intermediate substrate within the cavity such that the conductive bond pad of the second semiconductor die is aligned with the passage.Type: ApplicationFiled: August 28, 2002Publication date: January 9, 2003Inventor: Venkateshwaran Vaiyapuri
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Publication number: 20020184907Abstract: A cooling mechanism within an integrated circuit includes an internal pump for circulating thermally conductive fluid within closed loop channels. The cooling channels are embedded within an integrated circuit die, such as in interlevel dielectric layers between metal levels. The channels are formed by engineering deposition of a layer to line trenches and form continuous voids along the trenches. Exemplary heat pumps comprise cavities, formed in communication with the channels, covered by piezoelectric actuators. Preferably, the actuators are wired to act in sequence as a peristaltic pump, circulating the fluid within the channels. The channels are positioned to carry heat from active devices within the integrated circuit, and a heat sink carries heat from the die.Type: ApplicationFiled: July 23, 2001Publication date: December 12, 2002Inventors: Venkateshwaran Vaiyapuri, Fred Fishburn