Patents by Inventor Venkateswar Reddy Kowkutla
Venkateswar Reddy Kowkutla has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11923836Abstract: An example includes a circuit including a first AND gate including a first input terminal, a second input terminal, and an output terminal, a second AND gate including a first input terminal, a second input terminal, and an output terminal, and a third AND gate including a first input terminal, a second input terminal, and an output terminal. The circuit also includes an OR gate including a first input terminal coupled to the output terminal of the first AND gate, a second input terminal coupled to the output terminal of the second AND gate, a third input terminal coupled to the output terminal of the third AND gate, and an output terminal.Type: GrantFiled: June 25, 2020Date of Patent: March 5, 2024Assignee: Texas Instruments IncorporatedInventors: Venkateswar Reddy Kowkutla, Chunhua Hu, Erkan Bilhan, Sumant Dinkar Kale
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Patent number: 11770124Abstract: An integrated circuit includes: a clock domain having a clock domain input; and clock management logic coupled to the clock domain. The clock management logic includes: a PLL having a reference clock input and a PLL clock output; a divider having a divider input and a divider output, the divider input coupled to the PLL clock output; and bypass logic having a first clock input, a second clock input, a bypass control input, and a bypass logic output, the first clock input coupled to divider output, the second clock input coupled to the reference clock input, and the bypass logic output coupled to the clock domain input. The bypass logic selectively bypasses the PLL and divider responsive to a bypass control signal triggered by a reset signal. The reset signal also triggers a reset control signal delayed relative to the bypass control signal.Type: GrantFiled: October 29, 2021Date of Patent: September 26, 2023Assignee: Texas Instruments IncorporatedInventors: Jose Luis Flores, Venkateswar Reddy Kowkutla, Ramakrishnan Venkatasubramanian
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Publication number: 20230280784Abstract: An electronic device comprising one or more subcircuits configured to receive a clock signal, the clock signal configured to switch from a reference clock signal to a second clock signal based on a clock bypass signal, a timer configured to receive the reference clock signal and output an alignment signal based on the reference clock signal, wherein a frequency of the alignment signal is determined based on clock frequencies of the one or more subcircuits; a clock alignment module coupled to the timer and the one or more subcircuits and configured to receive the clock bypass signal, determine that the clock bypass signal has changed to switch the one or more subcircuits to the reference clock signal from the second clock signal, block the clock signal from being received by the one or more subcircuits, receive the alignment signal, and unblock the clock signal based on the alignment signal.Type: ApplicationFiled: May 15, 2023Publication date: September 7, 2023Inventors: Varun SINGH, Rejitha NAIR, John Chrysostom APOSTOL, Venkateswar Reddy KOWKUTLA, Santhanagopal RAGHAVENDRA
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Publication number: 20230259448Abstract: An integrated circuit includes a processor core configured to perform boot operations; and a microcontroller coupled to a processor core. The microcontroller includes: a set of microcontroller components; and a state machine coupled to the set of microcontroller components. The state machine is configured to perform self-test operations on the set of microcontroller components before the boot operations.Type: ApplicationFiled: April 24, 2023Publication date: August 17, 2023Inventors: Venkateswar Reddy KOWKUTLA, Rejitha NAIR
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Publication number: 20230168709Abstract: An electronic device comprising one or more subcircuits configured to receive a clock signal, the clock signal configured to switch from a reference clock signal to a second clock signal based on a clock bypass signal, a timer configured to receive the reference clock signal and output an alignment signal based on the reference clock signal, wherein a frequency of the alignment signal is determined based on clock frequencies of the one or more subcircuits; a clock alignment module coupled to the timer and the one or more subcircuits and configured to receive the clock bypass signal, determine that the clock bypass signal has changed to switch the one or more subcircuits to the reference clock signal from the second clock signal, block the clock signal from being received by the one or more subcircuits, receive the alignment signal, and unblock the clock signal based on the alignment signal.Type: ApplicationFiled: November 29, 2021Publication date: June 1, 2023Inventors: Varun SINGH, Rejitha NAIR, John Chrysostom APOSTOL, Venkateswar Reddy KOWKUTLA, Raghavendra SANTHANAGOPAL
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Patent number: 11662763Abstract: An electronic device comprising one or more subcircuits configured to receive a clock signal, the clock signal configured to switch from a reference clock signal to a second clock signal based on a clock bypass signal, a timer configured to receive the reference clock signal and output an alignment signal based on the reference clock signal, wherein a frequency of the alignment signal is determined based on clock frequencies of the one or more subcircuits; a clock alignment module coupled to the timer and the one or more subcircuits and configured to receive the clock bypass signal, determine that the clock bypass signal has changed to switch the one or more subcircuits to the reference clock signal from the second clock signal, block the clock signal from being received by the one or more subcircuits, receive the alignment signal, and unblock the clock signal based on the alignment signal.Type: GrantFiled: November 29, 2021Date of Patent: May 30, 2023Assignee: Texas Instruments IncorporatedInventors: Varun Singh, Rejitha Nair, John Chrysostom Apostol, Venkateswar Reddy Kowkutla, Raghavendra Santhanagopal
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Patent number: 11663111Abstract: An integrated circuit includes a processor core configured to perform boot operations; and a microcontroller coupled to a processor core. The microcontroller includes: a set of microcontroller components; and a state machine coupled to the set of microcontroller components. The state machine is configured to perform self-test operations on the set of microcontroller components before the boot operations.Type: GrantFiled: December 30, 2020Date of Patent: May 30, 2023Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Venkateswar Reddy Kowkutla, Rejitha Nair
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Patent number: 11509302Abstract: Disclosed embodiments include an electronic system with a power on reset (POR) circuit. The POR circuit includes first voltage detection circuitry to perform a first detection on a supply voltage and to output a first control signal in response to the first detection, second voltage detection circuitry to perform a second detection on the supply voltage and to output a second control signal in response to the second detection, and third voltage detection circuitry to perform a third detection on the supply voltage and to output at least one third control signal in response to the third detection. The POR circuit further has sequencing circuitry with a first input to receive the at least one third control signal and to output a reset signal in response to the at least one third control signal.Type: GrantFiled: October 26, 2020Date of Patent: November 22, 2022Assignee: Texas Instruments IncorporatedInventors: Chunhua Hu, Venkateswar Reddy Kowkutla, Charles Fuoco
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Publication number: 20220368444Abstract: A system on a chip (SOC) is configured to support multiple time domains within a time-sensitive networking (TSN) environment. TSN extends Ethernet networks to support a deterministic and high-availability communication on Layer 2 (data link layer of open system interconnect “OSI” model) for time coordinated capabilities such as industrial automation and control applications. Processors in a system may have an application time domain separate from the communication time domain. In addition, each type time domain may also have multiple potential time masters to drive synchronization for fault tolerance. The SoC supports multiple time domains driven by different time masters and graceful time master switching. Timing masters may be switched at run-time in case of a failure in the system. Software drives the SoC to establish communication paths through a sync router to facilitate communication between time providers and time consumers. Multiple time sources are supported.Type: ApplicationFiled: July 29, 2022Publication date: November 17, 2022Inventors: Chunhua HU, Venkateswar Reddy KOWKUTLA, Eric HANSEN, Denis BEAUDOIN, Thomas Anton LEYRER
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Patent number: 11405121Abstract: A system on a chip (SOC) is configured to support multiple time domains within a time-sensitive networking (TSN) environment. TSN extends Ethernet networks to support a deterministic and high-availability communication on Layer 2 (data link layer of open system interconnect “OSI” model) for time coordinated capabilities such as industrial automation and control applications. Processors in a system may have an application time domain separate from the communication time domain. In addition, each type time domain may also have multiple potential time masters to drive synchronization for fault tolerance. The SoC supports multiple time domains driven by different time masters and graceful time master switching. Timing masters may be switched at run-time in case of a failure in the system. Software drives the SoC to establish communication paths through a sync router to facilitate communication between time providers and time consumers. Multiple time sources are supported.Type: GrantFiled: August 27, 2019Date of Patent: August 2, 2022Assignee: Texas Instruments IncorporatedInventors: Chunhua Hu, Venkateswar Reddy Kowkutla, Eric Hansen, Denis Beaudoin, Thomas Anton Leyrer
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Publication number: 20220103179Abstract: An integrated circuit includes: a clock domain having a clock domain input; and clock management logic coupled to the clock domain. The clock management logic includes: a PLL having a reference clock input and a PLL clock output; a divider having a divider input and a divider output, the divider input coupled to the PLL clock output; and bypass logic having a first clock input, a second clock input, a bypass control input, and a bypass logic output, the first clock input coupled to divider output, the second clock input coupled to the reference clock input, and the bypass logic output coupled to the clock domain input. The bypass logic selectively bypasses the PLL and divider responsive to a bypass control signal triggered by a reset signal. The reset signal also triggers a reset control signal delayed relative to the bypass control signal.Type: ApplicationFiled: October 29, 2021Publication date: March 31, 2022Inventors: Jose Luis FLORES, Venkateswar Reddy KOWKUTLA, Ramakrishnan VENKATASUBRAMANIAN
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Patent number: 11269389Abstract: A functional safety POR system requires implementing voltage detectors and supervisory functions in a complex SOC. These features are implemented within the SOC without external components. Three stages of voltage monitoring are implemented to ensure redundancy.Type: GrantFiled: March 10, 2020Date of Patent: March 8, 2022Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Venkateswar Reddy Kowkutla, Chunhua Hu, Erkan Bilhan, Sumant Dinkar Kale
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Patent number: 11196424Abstract: An integrated circuit includes: a clock domain having a clock domain input; and clock management logic coupled to the clock domain. The clock management logic includes: a PLL having a reference clock input and a PLL clock output; a divider having a divider input and a divider output, the divider input coupled to the PLL clock output; and bypass logic having a first clock input, a second clock input, a bypass control input, and a bypass logic output, the first clock input coupled to divider output, the second clock input coupled to the reference clock input, and the bypass logic output coupled to the clock domain input. The bypass logic selectively bypasses the PLL and divider responsive to a bypass control signal triggered by a reset signal. The reset signal also triggers a reset control signal delayed relative to the bypass control signal.Type: GrantFiled: October 23, 2020Date of Patent: December 7, 2021Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Jose Luis Flores, Venkateswar Reddy Kowkutla, Ramakrishnan Venkatasubramanian
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Publication number: 20210209003Abstract: An integrated circuit includes a processor core configured to perform boot operations; and a microcontroller coupled to a processor core. The microcontroller includes: a set of microcontroller components; and a state machine coupled to the set of microcontroller components. The state machine is configured to perform self-test operations on the set of microcontroller components before the boot operations.Type: ApplicationFiled: December 30, 2020Publication date: July 8, 2021Inventors: Venkateswar Reddy KOWKUTLA, Rejitha NAIR
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Publication number: 20210211132Abstract: An integrated circuit includes: a clock domain having a clock domain input; and clock management logic coupled to the clock domain. The clock management logic includes: a PLL having a reference clock input and a PLL clock output; a divider having a divider input and a divider output, the divider input coupled to the PLL clock output; and bypass logic having a first clock input, a second clock input, a bypass control input, and a bypass logic output, the first clock input coupled to divider output, the second clock input coupled to the reference clock input, and the bypass logic output coupled to the clock domain input. The bypass logic selectively bypasses the PLL and divider responsive to a bypass control signal triggered by a reset signal. The reset signal also triggers a reset control signal delayed relative to the bypass control signal.Type: ApplicationFiled: October 23, 2020Publication date: July 8, 2021Inventors: Jose Luis FLORES, Venkateswar Reddy KOWKUTLA, Ramakrishnan VENKATASUBRAMANIAN
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Publication number: 20210044292Abstract: Disclosed embodiments include an electronic system with a power on reset (POR) circuit. The POR circuit includes first voltage detection circuitry to perform a first detection on a supply voltage and to output a first control signal in response to the first detection, second voltage detection circuitry to perform a second detection on the supply voltage and to output a second control signal in response to the second detection, and third voltage detection circuitry to perform a third detection on the supply voltage and to output at least one third control signal in response to the third detection. The POR circuit further has sequencing circuitry with a first input to receive the at least one third control signal and to output a reset signal in response to the at least one third control signal.Type: ApplicationFiled: October 26, 2020Publication date: February 11, 2021Inventors: Chunhua Hu, Venkateswar Reddy Kowkutla, Charles Fuoco
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Patent number: 10819334Abstract: Disclosed embodiments include an electronic system with a power on reset (POR) circuit. The POR circuit includes first voltage detection circuitry to perform a first detection on a supply voltage and to output a first control signal in response to the first detection, second voltage detection circuitry to perform a second detection on the supply voltage and to output a second control signal in response to the second detection, and third voltage detection circuitry to perform a third detection on the supply voltage and to output at least one third control signal in response to the third detection. The POR circuit further has sequencing circuitry with a first input to receive the at least one third control signal and to output a reset signal in response to the at least one third control signal.Type: GrantFiled: March 12, 2019Date of Patent: October 27, 2020Assignee: Texas Instruments IncorporatedInventors: Chunhua Hu, Venkateswar Reddy Kowkutla, Charles Fuoco
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Publication number: 20200328738Abstract: An example includes a circuit including a first AND gate including a first input terminal, a second input terminal, and an output terminal, a second AND gate including a first input terminal, a second input terminal, and an output terminal, and a third AND gate including a first input terminal, a second input terminal, and an output terminal. The circuit also includes an OR gate including a first input terminal coupled to the output terminal of the first AND gate, a second input terminal coupled to the output terminal of the second AND gate, a third input terminal coupled to the output terminal of the third AND gate, and an output terminal.Type: ApplicationFiled: June 25, 2020Publication date: October 15, 2020Inventors: Venkateswar Reddy Kowkutla, Chunhua Hu, Erkan Bilhan, Sumant Dinkar Kale
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Patent number: 10734993Abstract: The optimal operating voltage of a complex SoC may be influenced by process variations. The operating voltages may be dynamically adjusted for optimal performance. These adjustments require a dynamic reconfiguration of the voltage monitoring thresholds in the power on reset circuitry of the SoC.Type: GrantFiled: December 29, 2016Date of Patent: August 4, 2020Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Venkateswar Reddy Kowkutla, Chunhua Hu, Erkan Bilhan, Sumant Dinkar Kale
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Publication number: 20200209931Abstract: A functional safety POR system requires implementing voltage detectors and supervisory functions in a complex SOC. These features are implemented within the SOC without external components. Three stages of voltage monitoring are implemented to ensure redundancy.Type: ApplicationFiled: March 10, 2020Publication date: July 2, 2020Inventors: Venkateswar Reddy Kowkutla, Chunhua Hu, Erkan Bilhan, Sumant Dinkar Kale