Abstract: An apparatus and method for performing dual concurrent multiplications, subtraction/addition, and accumulation of packed data elements.

Abstract: An apparatus and method for multiplying packed real and imaginary components of complex numbers.

Abstract: An apparatus and method for performing dual concurrent multiplications of packed data elements.

Abstract: An apparatus and method for performing right-shifting operations on packed quadword data.

Abstract: An apparatus and method for performing a transform on complex data.

Abstract: An apparatus and method for performing dual concurrent multiplications of packed data elements.

Abstract: An apparatus and method for performing left-shifting operations on packed quadword data.

Abstract: An apparatus and method for multiplying packed real and imaginary components of complex numbers.

Abstract: Embodiments of instructions and methods of execution of said instructions and resources to execute said instructions are detailed. For example, in an embodiment, a processor comprising: decode circuitry to decode an instruction having fields for an opcode, a packed data source operand identifier, and a packed data destination operand identifier; and execution circuitry to execute the decoded instruction to convert a data element from a least significant packed data element position of the identified packed data source operand from a fixed-point representation to a floating point representation, store the floating point representation into a 32-bit least significant packed data element position of the identified packed data destination operand, and zero all remaining packed data elements of the identified packed data destination operand is described.

Abstract: Embodiments of an instruction, its operation, and executional support for the instruction are described. In some embodiments, a processor comprises decode circuitry to decode an instruction having fields for an opcode, a packed data source operand identifier, and a packed data destination operand identifier; and execution circuitry to execute the decoded instruction to convert a single precision floating point data element of a least significant packed data element position of the identified packed data source operand to a fixed-point representation, store the fixed-point representation as 32-bit integer and a 32-bit integer exponent in the two least significant packed data element positions of the identified packed data destination operand, and zero of all remaining packed data elements of the identified packed data destination operand.

Abstract: Methods and arrangements for evaluating a regular expression. Text strings are received. A regular expression is also received, the regular expression comprising a pattern for specifying and recognizing at least one text string from among the received text strings. There is generated, with respect to the received text strings, a data structure containing grams with positional information. The data structure is employed to evaluate the regular expression via identifying a subset of the text strings comprising at least one match for the given regular expression. Other variants and embodiments are broadly contemplated herein.

Abstract: A computer system and processor for elimination of move operations include circuits that obtain a computer instruction and bypass execution units in response to determining that the instruction includes a move operation that involves a transfer of data from a logical source register to a logical destination register. Instead of executing the move operation, the transfer of the data is performed by tracking changes in data dependencies of the source and the destination registers, and assigning a physical register associated with the source register to the destination register based on the dependencies.

Abstract: Methods and arrangements for evaluating a regular expression. Text strings are received. A regular expression is also received, the regular expression comprising a pattern for specifying and recognizing at least one text string from among the received text strings. There is generated, with respect to the received text strings, a data structure containing grams with positional information. The data structure is employed to evaluate the regular expression via identifying a subset of the text strings comprising at least one match for the given regular expression. Other variants and embodiments are broadly contemplated herein.

Abstract: A computer system and processor for elimination of move operations include circuits that obtain a computer instruction and bypass execution units in response to determining that the instruction includes a move operation that involves a transfer of data from a logical source register to a logical destination register. Instead of executing the move operation, the transfer of the data is performed by tracking changes in data dependencies of the source and the destination registers, and assigning a physical register associated with the source register to the destination register based on the dependencies.

Abstract: Methods and apparatus relating to speculatively decoding instruction lengths in order to increase instruction throughput are described. In an embodiment, instructions are speculatively decoded within a pipelined microprocessor architecture such that up to four instruction lengths may be decoded within a maximum of two processor clock cycles. Other embodiments are also disclosed.

Abstract: A virtual machine extension (VMX) architecture. More particularly, embodiments of the invention relate to a method and apparatus to enable single stepping of a guest application within a microprocessor or group of processing elements.