Abstract: A memory circuit includes a memory array comprising a first portion comprising a plurality of first memory cells, and a second portion comprising a plurality of second memory cells. The memory circuit includes an input/output (I/O) circuit physically disposed next to the memory array along a first lateral direction. The I/O circuit is operatively coupled to the first portion and the second portion through a first access line and a second access line, respectively. The memory circuit includes a first pre-charge circuit physically disposed opposite the first portion from the I/O circuit, and configured to charge the first access line prior to accessing the first memory cells. The memory circuit includes a second pre-charge circuit physically disposed opposite the second portion from the first pre-charge circuit, and configured to charge at least a portion of the second access line prior to accessing the second memory cells.

Abstract: An example system includes a controller having a first controller terminal, a second controller terminal, and a third controller terminal and digitally locked loop (DLL) circuitry having a first DLL terminal and a second DLL terminal, the first DLL terminal coupled to the first controller terminal. The system also includes first retimer circuitry having a first retimer terminal, and a second retimer terminal, and a third retimer terminal, the first retimer terminal coupled to the second DLL terminal and the second retimer terminal coupled to the second controller terminal and second retimer circuitry having a fourth retimer terminal, a fifth retimer terminal, and a sixth retimer terminal, the fourth retimer terminal coupled to the second DLL terminal and the fifth retimer terminal coupled to the third controller terminal.

Abstract: A memory device includes a memory array including a plurality of word lines, each of the plurality of word lines operatively coupled to a corresponding set of memory cells, and a controller operatively coupled to the memory array. The controller is configured to receive a first address signal indicating a first word line that is physically arranged with respect to the controller by a first distance, assert the first word line through a first signal with a first pulse width, receive a second address signal indicating a second word line that is physically arranged with respect to the controller by a second distance, assert the second word line through a second signal with a second pulse width, and adjust one of the first pulse width or the second pulse width based on the first distance and the second distance.

Abstract: A first network node, comprises a memory configured to store computer program code that includes first transmitting code configured to cause a processor to transmit, to a second network node, a bearer context modification request that includes an information element requesting a data usage report. The program code further includes first receiving code configured to cause the processor to receive, from the second network node in response to the information element included in the bearer context modification request, a bearer context modification response and a data usage report. The program code further includes forwarding code configured to cause at least one of said at least one processor to the data usage report to a third network node.

Abstract: A system and a method include monitoring a discharge temperature of a compressor of a powered system while the compressor is in an unpowered state, and changing the state of the compressor from the unpowered state to an unloaded powered state to start operation of the compressor responsive to the discharge temperature of the compressor reaching a first temperature threshold. The discharge temperature of the compressor is monitored for a first length of time while the compressor operates in the unloaded powered state. The state of the compressor is changed from the unloaded powered state to a loaded powered state responsive to the discharge temperature being within a first temperature range for the first length of time.

Abstract: An apparatus includes a first processor; and a memory having instructions stored thereon that, when executed by the first processor, cause the apparatus to monitor a flow of data packets on a network plane. The apparatus is also caused to calculate a packet rate of the flow of the data packets. The apparatus is further caused to compare the packet rate with a first threshold value. The apparatus is additionally caused to, in response to determining the packet rate is less than the first threshold value, cause an operating state of a second processor communicatively coupled with the apparatus to change from an active state to a sleep state.

Abstract: An example system includes a controller having a first controller terminal, a second controller terminal, and a third controller terminal and digitally locked loop (DLL) circuitry having a first DLL terminal and a second DLL terminal, the first DLL terminal coupled to the first controller terminal. The system also includes first retimer circuitry having a first retimer terminal, and a second retimer terminal, and a third retimer terminal, the first retimer terminal coupled to the second DLL terminal and the second retimer terminal coupled to the second controller terminal and second retimer circuitry having a fourth retimer terminal, a fifth retimer terminal, and a sixth retimer terminal, the fourth retimer terminal coupled to the second DLL terminal and the fifth retimer terminal coupled to the third controller terminal.

Abstract: Systems and circuits include an amplifier having an output; a switching circuit coupled to the output of the amplifier to provide a bias current to bias the amplifier; first current generating circuitry coupled to the switching circuit; and second current generating circuitry coupled to the output of the amplifier and to the switching circuit. In operation, the switching circuit provides the bias current, during a first time period, in response to a first signal generated by the first current generating circuitry, and provides the bias current, during a second time period, after the first time period, in response to a second signal generated by the second current generating circuitry.

Abstract: An example apparatus includes: digitally locked loop (DLL) circuitry coupled to a clock terminal and configured to generate a plurality of delayed clocks at a plurality of delayed clock terminals based on a reference clock of the clock terminal; first retimer circuitry coupled to the plurality of delayed clock terminals, a first data terminal, and a second data terminal, the first retimer circuitry configured to delay and serialize data of the first data terminal and the second data terminal using at least one of the delayed clocks of the plurality of delayed clock terminals; and second retimer circuitry coupled to the plurality of delayed clock terminals, a third data terminal, and a fourth data terminal, the second retimer circuitry configured to delay and serialize data of the third data terminal and the fourth data terminal.

Abstract: A semiconductor device includes a first memory array, a first bit line, a second memory array, a second bit line, a first conductive line and a first control circuit. The first bit line crosses over and is coupled to the first memory array, and extends along a first direction. The second bit line crosses over the second memory array, and is coupled to the first bit line. The first conductive line crosses over the second memory array and a part of the first memory array, and is configured to operate as a part of a first capacitor. The first control circuit is configured to couple the first conductive line to the second bit line when the first memory array is written.

Abstract: A semiconductor device includes a first memory bank, a second memory bank and a first write driver. The first memory bank is coupled to a plurality of first data lines, and configured to operate according to a first data signal. The second memory bank is configured to operate according to the first data signal. The first write driver is disposed between the first memory bank and the second memory bank, and configured to adjust a voltage level of one of the plurality of first data lines when the first memory bank is written according to the first data signal.

Abstract: A vehicle braking system includes one or more traction motors and an electrical device configured to be electrically coupled with the one or more traction motors. The one or more traction motors are configured to propel a vehicle and to generate electric power during rollback of the vehicle down a grade. The electrical device is configured to consume the electric power generated from the rollback of the vehicle by performing work with the electric power during the rollback of the vehicle.

Abstract: An example apparatus includes: digitally locked loop (DLL) circuitry coupled to a clock terminal and configured to generate a plurality of delayed clocks at a plurality of delayed clock terminals based on a reference clock of the clock terminal; first retimer circuitry coupled to the plurality of delayed clock terminals, a first data terminal, and a second data terminal, the first retimer circuitry configured to delay and serialize data of the first data terminal and the second data terminal using at least one of the delayed clocks of the plurality of delayed clock terminals; and second retimer circuitry coupled to the plurality of delayed clock terminals, a third data terminal, and a fourth data terminal, the second retimer circuitry configured to delay and serialize data of the third data terminal and the fourth data terminal.

Abstract: Systems and methods control operation of multiple compressors of a multi-compressor assembly on a vehicle. A controller determines a leak rate of a brake system of a vehicle. The controller changes a pressure threshold at which one or more compressors are activated to supply gas to the brake system based on the leak rate. The controller activates at least a first compressor of the one or more compressors to increase a gas pressure of the brake system based on the gas pressure of the brake system falling below the pressure threshold that is changed.

Abstract: Systems and circuits include an amplifier having an output; a switching circuit coupled to the output of the amplifier to provide a bias current to bias the amplifier; first current generating circuitry coupled to the switching circuit; and second current generating circuitry coupled to the output of the amplifier and to the switching circuit. In operation, the switching circuit provides the bias current, during a first time period, in response to a first signal generated by the first current generating circuitry, and provides the bias current, during a second time period, after the first time period, in response to a second signal generated by the second current generating circuitry.

Abstract: The invention relates to a method for the removal of protein and other impurities from microbial capsular polysaccharides. More particularly, the present invention relates to isolation of microbial capsular polysaccharides in pure form after removal of protein and other impurities.

Abstract: Embodiments include a multi-tenant cloud-based identity management system for a plurality of tenants. Embodiments include a global database providing a first set of resources to the plurality of tenants and a plurality of tenant databases, each tenant database providing a second set of resources to one of the plurality of tenants. Embodiments further include a plurality of resources accessible by the tenants and an automated upgrade framework for upgrading the global database and the tenant databases in response to an upgrade of a first release of the system to a second release of the system. For the automated upgrade framework, embodiments determine resource changes between the first release and the second release, generate an upgrade patch based on the resource changes and apply the upgrade patch to the global database.

Abstract: Embodiments operate a multi-tenant cloud system. At a first data center, embodiments authenticate a first client corresponding to a first tenant ID and store resources that correspond to the first client, the first data center in communication with a second data center that is configured to authenticate the first client and replicate the resources. The first data center receives an Application Programming Interface (“API”) request for the first client corresponding to a change to the resources, and generates a change log and corresponding change event message in response to the API request. Embodiments compute a first hash corresponding to the first tenant ID of the change log to determine a first partition of a first queue at the first data center. The first data center pushes the change event message to the second data center via an API call.

Abstract: In an example, a system includes an amplifier configured to produce a bandgap voltage reference. The system also includes a current source configured to provide a current to bias the amplifier. The system includes a switching circuit configured to receive a first current replica signal and a second current replica signal, the switching circuit further configured to cause the current source to provide the current to bias the amplifier based on either the first current replica signal or the second current replica signal.

Abstract: In an example, a system includes an amplifier configured to produce a bandgap voltage reference. The system also includes a current source configured to provide a current to bias the amplifier. The system includes a switching circuit configured to receive a first current replica signal and a second current replica signal, the switching circuit further configured to cause the current source to provide the current to bias the amplifier based on either the first current replica signal or the second current replica signal.