Patents by Inventor Venkidesh KRISHNA IYER

Venkidesh KRISHNA IYER has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Network and edge acceleration tile (NEXT) architecture
    Patent number: 11983131
    Abstract: Examples described herein include a system comprising: a processing unit package comprising: at least one core and at least one offload processing device communicatively coupled inline between the at least one core and a network interface controller, the at least one offload processing device configurable to perform packet processing. In some examples, the at least one offload processing device is to allow mapping of packet processing pipeline stages of networking applications among software running on the at least one core and the at least one offload processing device to permit flexible entry, exit, and re-entry points among the at least one core and the at least one offload processing device.
    Type: Grant
    Filed: December 26, 2020
    Date of Patent: May 14, 2024
    Assignee: Intel Corporation
    Inventors: Patrick G. Kutch, Andrey Chilikin, Niall D. McDonnell, Brian A. Keating, Naveen Lakkakula, Ilango S. Ganga, Venkidesh Krishna Iyer, Patrick Fleming, Lokpraveen Mosur
  • PACKET TRANSMISSION SCHEDULING FAIRNESS
    Publication number: 20220006750
    Abstract: Examples described herein relate to a network interface device comprising a packet transmission scheduler. In some examples, the packet transmission scheduler is to: perform packet transmit arbitration among nodes, wherein based on a first node of the nodes having transmission paused by flow control, the perform packet transmit arbitration among nodes comprises retain relative priority of a packet departure time for the first node with respect to a second packet departure time associated with a second node of the nodes during a duration of flow control. In some examples, retaining relative priority of a packet departure time for the first node with respect to a second packet departure time associated with a second node of the nodes during a duration of flow control comprises adjust the packet departure time and the second packet departure time to stay within a time window but not rollover.
    Type: Application
    Filed: September 14, 2021
    Publication date: January 6, 2022
    Inventors: Sarig LIVNE, Noam ELATI, Hemanth KRISHNAN, Venkidesh KRISHNA IYER, Adam CONYERS, Michael G. LEFEVRE
  • NETWORK AND EDGE ACCELERATION TILE (NEXT) ARCHITECTURE
    Publication number: 20210117360
    Abstract: Examples described herein include a system comprising: a processing unit package comprising: at least one core and at least one offload processing device communicatively coupled inline between the at least one core and a network interface controller, the at least one offload processing device configurable to perform packet processing. In some examples, the at least one offload processing device is to allow mapping of packet processing pipeline stages of networking applications among software running on the at least one core and the at least one offload processing device to permit flexible entry, exit, and re-entry points among the at least one core and the at least one offload processing device.
    Type: Application
    Filed: December 26, 2020
    Publication date: April 22, 2021
    Inventors: Patrick G. KUTCH, Andrey CHILIKIN, Niall D. MCDONNELL, Brian A. KEATING, Naveen LAKKAKULA, Ilango S. GANGA, Venkidesh KRISHNA IYER, Patrick FLEMING, Lokpraveen MOSUR