Abstract: A high Q bandpass filter (102) is tuned by applying a transient (204) to the filter to cause it to ring. The ringing of the filter produces an output damped oscillatory waveform (206) whose zero crossings (208) are converted to a pulse train (210) and counted in a digital counter (112) to a predetermined number n. The output (214) of the counter is compared to an accurate timing signal (216) which has a time duration equal to the time of n pulses when the filter is accurately tuned. The output of the comparator (118) is applied to an integrator (122) to generate a control signal V.sub.c to tune the filter. The high frequency tuning problem is thus converted to a low frequency, time domain problem which is readily implemented.

Abstract: A method and apparatus for reducing aperture uncertainty and kick-back noise in high speed comparators is disclosed. The disclosed method is used in a comparator for comparing a first signal (INP) and a second signal (INM) and having a track mode and a regenerative mode of operation. The steps of this method are as follows. A first input current representing the first signal is switched through a first output node (OUTP) during the track mode and a second input current representing the second signal is switched through a second output node (OUTM) during the track mode. During the regenerative mode, approximately half of the first input current is switched through the first output node (OUTP) and approximately half of the first input current is switched through the second output node (OUTM). Also during the regenerative mode, approximately half of the second input current is switched through the first output node and approximately half of the second input current is switched through the second output node.

Abstract: A transconductance-capacitor filter system (8) is provided which includes a transconductance-capacitor filter 10 having a first node (NODE 1) and a second node (NODE 2). A current sensor circuit 12 is coupled to the first node (NODE 1) and the second node (NODE 2).

Abstract: A logic gate with highly matched output rise and fall times is provided which includes at least one stacked transistor pair (24) and at least one complementary stacked transistor pair (30) connected in parallel across at least one node (NODE 1 and NODE 2).

Abstract: A current duplicator (10) is provided for receiving a calibration current and providing an output current to a load (10). Current duplicator (10) includes a transconductor (14) having a differentially coupled input with a parasitic capacitance for storing a differential voltage during a supply period. This parasitic capacitance also converts a difference current into the voltage during a feedback period. The difference current is equal to the difference between the output current and the calibration current. Transconductor (14) converts the voltage into the output current. The current duplicator also includes a first switch network for coupling the output current to the load (12) during the supply period. The output current remains within a predetermined amount from the calibration current during the supply period. A second switch network feeds back the difference current to the input during the feedback period at least until the output current becomes substantially equal to the calibration current.

Abstract: A rectangular-to-sine wave converter circuit (10) is provided that comprises a flip-flop (12) that provides for a square wave and an inverse square wave circuit with fifty percent duty cycles. Each of the square wave signals is passed through a multi-stage low pass filter. The stages of the low pass filters are separated by buffers (26) and (32). The common mode voltage of the output signals at output nodes (40) and (44) are adjusted with respect to an arbitrary bias voltage V.sub.bias by using bias resistors (42) and (68).

Abstract: A system (10) is disclosed which tunes a result (14) of a process (12) relative to a reference (16). The system (10) uses two control parameters (C.sub.1 and C.sub.2) which are controlled by a switch (20). The control parameters (C.sub.1 and C.sub.2) are controlled such that only one of the two is acting upon the process (12) to alter the result (14) at any one time.

Abstract: A common-mode feedback circuit comprises a reference generator (12) for generating a signal corresponding to a desired common-mode operating point connected to a common-mode bias circuit (14) for generating a second signal corresponding to the common-mode operating point of the outputs (V.sub.out.sup.+, V.sub.out.sup.-) of the fully differential operational amplifier. In the preferred embodiment, the common-mode bias circuit (14) includes a sensing circuit (58) comprising two MOS transistors (60, 62) having sources and drains connected together. The MOS transistors (60, 62) operate in the ohmic region to provide a variable load responsive to the output signals (V.sub.out.sup.+, V.sub.out.sup.-) connected to their gates.