Abstract: A Reed-Solomon decoder circuit includes: a syndrome calculator circuit to compute syndrome values for a first codeword and a second codeword sequentially supplied to the syndrome calculator circuit, where last symbols of the first codeword overlap with first symbols of the second codeword during an overlap clock cycle between: a first plurality of non-overlap clock cycles during which the first codeword is supplied to the syndrome calculator circuit; and a second plurality of non-overlap clock cycles during which the second codeword is supplied to the syndrome calculator circuit; an error locator and error evaluator polynomial calculator circuit; an error location and error value calculator circuit; an error counter; and an error corrector circuit to correct the errors in the first codeword and the second codeword based on error counts and the error magnitudes computed by an error evaluator circuit.

Abstract: A multi-port, multi-mode Reed Solomon (RS) forward error correction system includes a plurality of data in lines, each associated with a data port. The system includes a syndrome block (SDM) that has a plurality of syndrome slices and a SDM switching logic. An input of a SDM slice couples with a data in line from the plurality of data in lines. The switching logic couples with an interface port width (IFW) line a mode line. The IFW line identifies a number of data in lines tied together and the mode line to identify a RS mode. A reformulated inversionless Berlekamp-Massey (RiBM) block has a plurality of RiBM slices and a RiBM switching logic. A Chien Forney (ChFr) block has a plurality of ChFr slices. An error evaluation magnitude (ErEval) block has a plurality of ErEval slices. A plurality of adders couple with an output of a corresponding ErEval slice.

Abstract: A method for error correction comprises receiving data at a first device, and decoding, by decoder circuitry of the first device, the data. Decoding the data comprises determining a first error location within the data, and determining a first error magnitude within the data in parallel with determining the first error location. Decoding the data further comprises performing error correction to generate the decoded data based on the first error location and the first error magnitude. The method further comprises transmitting the decoded data to a second device.

Abstract: A multi-port, multi-mode Reed Solomon (RS) forward error correction system includes a plurality of data in lines, each associated with a data port. The system includes a syndrome block (SDM) that has a plurality of syndrome slices and a SDM switching logic. An input of a SDM slice couples with a data in line from the plurality of data in lines. The switching logic couples with an interface port width (IFW) line a mode line. The IFW line identifies a number of data in lines tied together and the mode line to identify a RS mode. A reformulated inversionless Berlekamp-Massey (RiBM) block has a plurality of RiBM slices and a RiBM switching logic. A Chien Forney (ChFr) block has a plurality of ChFr slices. An error evaluation magnitude (ErEval) block has a plurality of ErEval slices. A plurality of adders couple with an output of a corresponding ErEval slice.

Abstract: A method for error correction comprises receiving data at a first device, and decoding, by decoder circuitry of the first device, the data. Decoding the data comprises determining a first error location within the data, and determining a first error magnitude within the data in parallel with determining the first error location. Decoding the data further comprises performing error correction to generate the decoded data based on the first error location and the first error magnitude. The method further comprises transmitting the decoded data to a second device.

Abstract: A dual-mode Reed-Solomon decoder is configured to perform error correction for two different encoding schemes. The decoder includes a syndrome calculator block, a key equation solver block, a polynomial evaluation block, and an error correction block. The syndrome calculator block receives encoded input data and calculates syndromes, with the number of calculated syndromes based on the selected decoding mode. The key equation solver block calculates an error locator polynomial and an error evaluator polynomial for the encoded input data, with the degree of the polynomials based on the selected decoding mode. The polynomial evaluation block identifies error locations and magnitudes in the encoded data, with an array of constants input to the block based on the selected decoding mode. The error correction block decodes the encoded input data based on the identified error locations and error magnitudes.

Abstract: A dual-mode Reed-Solomon decoder is configured to perform error correction for two different encoding schemes. The decoder includes a syndrome calculator block, a key equation solver block, a polynomial evaluation block, and an error correction block. The syndrome calculator block receives encoded input data and calculates syndromes, with the number of calculated syndromes based on the selected decoding mode. The key equation solver block calculates an error locator polynomial and an error evaluator polynomial for the encoded input data, with the degree of the polynomials based on the selected decoding mode. The polynomial evaluation block identifies error locations and magnitudes in the encoded data, with an array of constants input to the block based on the selected decoding mode. The error correction block decodes the encoded input data based on the identified error locations and error magnitudes.

Abstract: Low-power, easily scalable architectures for high-speed data handling are critical to modern circuits and systems. Successful architectures must provide efficient data storage and efficient/flexible data retrieval with low power consumption. Data encoding, including that achieved with turbo codes, have data streams split into a sequence of even and odd data bits. These bits are written into multiple single-port memories so that the writing alternates between memories. Scheduling for the reading and writing is performed to avoid conflicts and give priority to the read operations.

Abstract: Metal and metal oxide nanoparticles can be prepared via a simple synthesis by using a hydrolysable gallotannin, such as tannic acid, to reduce a metal precursor compound and to act as a stabilizer for the resultant nanoparticles. By controlling the molar ratio of hydrolysable gallotannin to metal precursor and/or the initial pH of the reagents one can achieve control over the size and polydispersity of the resultant nanoparticles. In particular, the controlled addition of a metal precursor into a solution of the hydrolysable gallotannin, as described herein, can yield small nanoparticles, for example 1 nm to 40 nm diameter nanoparticles, with low polydispersity. The methods disclosed herein can be performed at room temperature.

Abstract: Metal and metal oxide nanoparticles can be prepared via a simple synthesis by using a hydrolysable gallotannin, such as tannic acid, to reduce a metal precursor compound and to act as a stabilizer for the resultant nanoparticles. By controlling the molar ratio of hydrolysable gallotannin to metal precursor and/or the initial pH of the reagents one can achieve control over the size and polydispersity of the resultant nanoparticles. In particular, the controlled addition of a metal precursor into a solution of the hydrolysable gallotannin, as described herein, can yield small nanoparticles, for example 1 nm to 40 nm diameter nanoparticles, with low polydispersity. The methods disclosed herein can be performed at room temperature.

Abstract: A micro electronic component, preferably in the form of an electronic memory, includes the use of clusters as an electronic memory. Also disclosed as part of the present invention is a method for fabricating a micro electronic component. The present invention contemplates fabrication of an especially compact electronic memory that works especially with single-electron transistors or single-electronic transfers. According to the present invention, clusters with a metallic cluster nucleus are arranged in parallel grooves essentially in lines or rows and are connected individually to first and second connecting electrodes, such that individually the clusters can be electrically modified or polled independently of each other.

Abstract: A micro electronic component, preferably in the form of an electronic memory, includes the use of clusters as an electronic memory. Also disclosed as part of the present invention is a method for fabricating a micro electronic component. The present invention contemplates fabrication of an especially compact electronic memory that works especially with single-electron transistors or single-electronic. transfers. According to the present invention, clusters with a metallic cluster nucleus are arranged in parallel grooves essentially in lines or rows and are connected individually to first and second connecting electrodes, such that individually the clusters can be electrically modified or polled independently of each other.

Abstract: The self-assembly of a close-packed, highly-ordered monolayers of molecularly protected nanoparticles on an assembly surface is disclosed. Also disclosed is the transfer of a nanoparticle monolayer from an assembly surface to a transfer surface. The transfer of a monolayer or multilayer structure of nanoparticles from a transfer surface to a substrate by conformal contact of the transfer surface with the substrate is disclosed. Also disclosed is the removal of protective molecules from nanoparticle cores by exposure to an oxidizing atmosphere (optionally in the presence of UV radiation). The exchange of protective molecules in molecularly protected nanoparticles with other molecules is also disclosed.