Abstract: For example, analog pixel circuitry may include a first input to input an analog pixel signal of the pixel; Sample and Hold (SH) circuitry to provide an analog sample of the pixel based on the analog pixel signal; one or more second inputs to input analog samples of one or more binning pixels, respectively; a plurality of capacitors having capacitor outputs connected to a common output terminal, wherein a capacitor input of a first capacitor is connected to an input terminal to input the analog sample of the pixel from the SH circuitry, wherein capacitor inputs of one or more second capacitors are connected to the one or more second inputs, respectively; and an amplifier configured to provide an amplified analog signal by amplifying an analog signal from the common output terminal.

Abstract: For example, analog pixel circuitry may include a first input to input an analog pixel signal of the pixel; Sample and Hold (SH) circuitry to provide an analog sample of the pixel based on the analog pixel signal; one or more second inputs to input analog samples of one or more binning pixels, respectively; a plurality of capacitors having capacitor outputs connected to a common output terminal, wherein a capacitor input of a first capacitor is connected to an input terminal to input the analog sample of the pixel from the SH circuitry, wherein capacitor inputs of one or more second capacitors are connected to the one or more second inputs, respectively; and an amplifier configured to provide an amplified analog signal by amplifying an analog signal from the common output terminal.

Abstract: An apparatus generally having an interface circuit and a processor. The interface circuit may have a queue and a connection to a memory. The processor may have a pipeline. The processor is generally configured to (i) place an address in the queue in response to processing a first instruction in a first stage of the pipeline, (ii) generate a flag by processing a second instruction in a second stage of the pipeline, the second instruction may be processed in the second stage after the first instruction is processed in the first stage, and (iii) generate a signal based on the flag in a third stage of the pipeline. The third stage may be situated in the pipeline after the second stage. The interface circuit is generally configured to cancel the address from the queue without transferring the address to the memory in response to the signal having a disabled value.