Abstract: A data storage device includes a memory device and a controller coupled to the memory device. The controller is configured to generate a first mapping portion and a second mapping portion, where the first mapping portion and the second mapping portion correspond to a same data set, and where the first mapping portion and the second mapping portion includes one or more parity bits, receive an update for the same data set, update the first mapping portion and the second mapping portion based on the update, where the second mapping portion is updated non-concurrently to updating the first mapping portion, and where the updating includes flipping a parity bit of the one or more parity bits, and determine whether the one or more parity bits of the first mapping portion matches the one or more parity bits of the second mapping portion.

Abstract: A data storage device includes a memory device and a controller coupled to the memory device. The controller is configured to generate a first mapping portion and a second mapping portion, where the first mapping portion and the second mapping portion correspond to a same data set, and where the first mapping portion and the second mapping portion includes one or more parity bits, receive an update for the same data set, update the first mapping portion and the second mapping portion based on the update, where the second mapping portion is updated non-concurrently to updating the first mapping portion, and where the updating includes flipping a parity bit of the one or more parity bits, and determine whether the one or more parity bits of the first mapping portion matches the one or more parity bits of the second mapping portion.

Abstract: The present disclosure generally relates to estimating when data to be written will be read or re-written prior to actually writing the data to the memory device. The estimating can be used to smartly route the data to the appropriate memory location at the writing stage or to evict the data from a hot memory location to a colder memory location. To perform the estimating, typical traces or data may be used as may the metadata of the data. Separating data according to the data “temperature” (i.e. the expected access time and frequency), and usage to optimize the SLC partition usage has meaningful impact on several storage metrics such as performance and endurance.

Abstract: A data storage device includes a memory device and a controller coupled to the memory device. The controller is configured to relocate first valid data from a first source block to a destination block, relocate second valid data from a second source block to the destination block, determine that the destination block is closed, re-mark the first and second source block with a second indication, and erase the source blocks that have the second indication. The first source block and the second source block are marked with a first indication after each respective data is relocated. The first indication indicates that the source block cannot be freed. The second indication indicates that the destination block is closed and the associated source blocks can be erased. Prior to closing the destination block, parity data may be generated for the data of the destination block and programmed to the destination block.

Abstract: A storage system has volatile memory for use as a cache and can extend the available caching space by using a host memory buffer (HMB) in a host. However, because accesses to the HMB involve going through a host interface, there may be latencies in accessing the HMB, To reduce access latencies, the storage system views the volatile memory and the HMB as a two-level cache. In one use case, the storage system decides whether to store a logical-to-physical address table in the volatile memory or in the HMB based on a prediction of the likelihood that the table will be updated. If the likelihood for an update is above a threshold, the table is stored in the volatile memory, thereby eliminating the access latencies that would be encountered if the table needs to be updated and is stored in the HMB.

Abstract: A storage system has volatile memory for use as a cache and can extend the available caching space by using a host memory buffer (HMB) in a host. However, because accesses to the HMB involve going through a host interface, there may be latencies in accessing the HMB, To reduce access latencies, the storage system views the volatile memory and the HMB as a two-level cache. In one use case, the storage system decides whether to store a logical-to-physical address table in the volatile memory or in the HMB based on a prediction of the likelihood that the table will be updated. If the likelihood for an update is above a threshold, the table is stored in the volatile memory, thereby eliminating the access latencies that would be encountered if the table needs to be updated and is stored in the HMB.

Abstract: A system and method is disclosed for providing zero data in response to a host data read directed to a logical address that is not associated with valid data. The system may be a non-volatile memory system including non-volatile memory and a controller configured to determine whether a logical address in a read command is associated with valid data. The controller may be configured to generate, store in non-volatile memory and retrieve from that non-volatile memory a zero data entry. The controller may also be configured to include any associated encryption key or logical address in the generation of the zero data in order to satisfy data path protection and/or encryption requirements for the non-volatile memory system. Storage and retrieval of the zero data may be via the non-volatile memory array or only the data latches of the non-volatile memory.

Abstract: A system and method is disclosed for managing a non-volatile memory system having a multi-processor controller. The controller may be configured with a plurality of processors and a shared data queue in a cyclic data buffer. Each of the plurality of processors may manage a separate pointer pointing to a different entry of the shared data queue and multiple ones of the processors may concurrently access or update entries in the shared data queue.

Abstract: A storage device utilizing read look ahead (RLA) may utilize auxiliary or spare latches as a RLA cache for storing pre-fetch data. The RLA may predict the next commands and do a speculative read to the flash using the latches for RLA storage. The auxiliary/spare latches may be present on a plane or die of non-volatile memory and may be different from the transfer data latch (XDL) that transfers data from the memory and the host. When the XDL is backed up, sense commands may still be performed and the data is stored in the auxiliary latches before being transferred with the XDL.

Abstract: A data storage device includes a non-volatile memory, a temperature sensor, and temperature calibration circuitry coupled to the temperature sensor. The temperature calibration circuitry is configured to cause memory operations to be performed on storage elements of the non-volatile memory, to determine a temperature metric based on temperature readings from the temperature sensor in response to initiation of the memory operations, and to modify a temperature threshold based on the temperature metric.

Abstract: A data storage device includes a non-volatile memory, a temperature sensor, and temperature calibration circuitry coupled to the temperature sensor. The temperature calibration circuitry is configured to cause memory operations to be performed on storage elements of the non-volatile memory, to determine a temperature metric based on temperature readings from the temperature sensor in response to initiation of the memory operations, and to modify a temperature threshold based on the temperature metric.

Abstract: A system and method is disclosed for managing a non-volatile memory system having a multi-processor controller. The controller may be configured with a plurality of processors and a shared data queue in a cyclic data buffer. Each of the plurality of processors may manage a separate pointer pointing to a different entry of the shared data queue and multiple ones of the processors may concurrently access or update entries in the shared data queue.

Abstract: A system and method is disclosed for providing zero data in response to a host data read directed to a logical address that is not associated with valid data. The system may be a non-volatile memory system including non-volatile memory and a controller configured to determine whether a logical address in a read command is associated with valid data. The controller may be configured to generate, store in non-volatile memory and retrieve from that non-volatile memory a zero data entry. The controller may also be configured to include any associated encryption key or logical address in the generation of the zero data in order to satisfy data path protection and/or encryption requirements for the non-volatile memory system. Storage and retrieval of the zero data may be via the non-volatile memory array or only the data latches of the non-volatile memory.

Abstract: A storage device utilizing read look ahead (RLA) may utilize auxiliary or spare latches as a RLA cache for storing pre-fetch data. The RLA may predict the next commands and do a speculative read to the flash using the latches for RLA storage. The auxiliary/spare latches may be present on a plane or die of non-volatile memory and may be different from the transfer data latch (XDL) that transfers data from the memory and the host. When the XDL is backed up, sense commands may still be performed and the data is stored in the auxiliary latches before being transferred with the XDL.

Abstract: A system and method for I/O optimization in a multi-queued environment are provided. In one embodiment, a host is provided that sorts commands into a plurality of queues, wherein a command is sorted based on its data characteristic. The host receives a read request from a storage module for commands in the plurality of queues and provides the storage module with the requested commands. In another embodiment, a storage module is provided that processes commands from a host based on the data characteristic of the queue that stored the command on the host. In another embodiment, a storage module sorts command completions into a plurality of queues, wherein a command completion is sorted based on its resulting status code.

Abstract: A system and method for I/O optimization in a multi-queued environment are provided. In one embodiment, a host is provided that sorts commands into a plurality of queues, wherein a command is sorted based on its data characteristic. The host receives a read request from a storage module for commands in the plurality of queues and provides the storage module with the requested commands. In another embodiment, a storage module is provided that processes commands from a host based on the data characteristic of the queue that stored the command on the host. In another embodiment, a storage module sorts command completions into a plurality of queues, wherein a command completion is sorted based on its resulting status code.