Abstract: This application discloses simulating a circuit design with a test bench and determining an expression coverage in the circuit design by the test bench with a rapid expression coverage process. The rapid expression coverage process can include dividing an expression in the circuit design into multiple sub-expressions, and separately evaluating each of the multiple sub-expressions during simulation of the circuit design to detect whether first operands in the corresponding sub-expressions receive each available input state, while second operands in the corresponding sub-expressions are in a non-masking state. The rapid expression coverage can generate an expression coverage metric to indicate whether expressions in the circuit design were covered by the test bench during the simulation of the circuit, for example, without having to generate truth-tables that include each possible input vector for each expression.

Abstract: This application discloses simulating a circuit design with a test bench and determining an expression coverage in the circuit design by the test bench with a rapid expression coverage process. The rapid expression coverage process can include dividing an expression in the circuit design into multiple sub-expressions, and separately evaluating each of the multiple sub-expressions during simulation of the circuit design to detect whether first operands in the corresponding sub-expressions receive each available input state, while second operands in the corresponding sub-expressions are in a non-masking state. The rapid expression coverage can generate an expression coverage metric to indicate whether expressions in the circuit design were covered by the test bench during the simulation of the circuit, for example, without having to generate truth-tables that include each possible input vector for each expression.