Abstract: A modeling system includes a processor with software that performs static timing analysis (STA) on a design model. STA software executes a static timing analysis (STA) run with shortened clock cycles to model full cycle clock variability. Designers or other entities interpret the results of the shortened STA run data by performing modeling on the output data to generate slack data for design model data paths. STA software executes an STA run with an extended clock cycle to automatically separate half cycle data path (HCDP) slack data from full cycle data path (FCDP) slack data. The full and half cycle clock variability method may automatically adjust slack data for all half cycle data paths (HCDP)s to account for the additional half cycle variation (AHCV) and half cycle clock edge variability that may penalize the design model results in a real hardware implementation.

Abstract: In the course of unit timing, there exists the possibility for a non-compute (N/C) on a particular net in an IC chip design, which could be caused by numerous things, including but not limited to a pin being tied to power, a floating output, or invalid timing test for a given phase at a test point. A process automatically verifies that all non-computes are understood and exist for valid reasons, in order to ensure all necessary paths are being timed. The process takes a conventional Comprehensive Report output of a unit timing run and generates macro specific N/C reports for designers to review and sign off on.

Abstract: A modeling system includes a processor with software that performs static timing analysis (STA) on a design model. STA software executes a static timing analysis (STA) run with shortened clock cycles to model full cycle clock variability. Designers or other entities interpret the results of the shortened STA run data by performing modeling on the output data to generate slack data for design model data paths. STA software executes an STA run with an extended clock cycle to automatically separate half cycle data path (HCDP) slack data from full cycle data path (FCDP) slack data. The full and half cycle clock variability method may automatically adjust slack data for all half cycle data paths (HCDP)s to account for the additional half cycle variation (AHCV) and half cycle clock edge variability that may penalize the design model results in a real hardware implementation.

Abstract: In the course of unit timing, there exists the possibility for a non-compute (N/C) on a particular net in an IC chip design, which could be caused by numerous things, including but not limited to a pin being tied to power, a floating output, or invalid timing test for a given phase at a test point. A process automatically verifies that all non-computes are understood and exist for valid reasons, in order to ensure all necessary paths are being timed. The process takes a conventional Comprehensive Report output of a unit timing run and generates macro specific N/C reports for designers to review and sign off on.