Abstract: A method for handling a request of storage on a serial fabric comprising formatting an address for communication on a serial fabric into a plurality of fields including a field comprising at least one set selection bit and a field comprising at least one tag bit. The address is communicated on the serial fabric with the field comprising the at least one set selection bit communicated first.

Abstract: A video sequence is enhanced by selecting a reference video frame and at least one auxiliary video frame from the video sequence. The information from the reference frame and the auxiliary frame are combined based on measurements of the displacement of objects between the reference frame and each of the auxiliary video frames. Video and multimedia presentations are then generated using the enhanced video frame combining information from the reference video frame and the at least one auxiliary video frame.

Abstract: A method of performing operations in a computer system, computer system, and related method of compilation, are disclosed. In one embodiment, the method of performing includes providing compiled code having at least one thread, where each of the at least one thread includes a respective plurality of blocks and each respective block includes a respective pre-fetch component and a respective execute component. The method also includes performing a first pre-fetch component from a first block of a first thread of the at least one thread, performing a first additional component after the first pre-fetch component has been performed, and performing a first execute component from the first block of the first thread. The first execute component is performed after the first additional component has been performed, and the first additional component is from either a second thread or another block of the first thread that is not the first block.

Abstract: A method for maintaining cache coherence comprises coordinating operations among a plurality of processors distributed among a plurality of nodes coupled by an interconnect fabric and managing cache coherence in a plurality of memory directories respectively associated with the processor plurality in combination with a node controller directory cache associated with a node controller coupled between the processor plurality and the interconnect fabric. The method further comprises maintaining memory coherence directory information comprising identifying processors within a node in a first portion of bits of a memory directory entry coupled to an associated processor in the node and identifying subsets of processors external to the node in the system in a second portion of bits.

Abstract: A method of performing operations in a computer system, computer system, and related method of compilation, are disclosed. In one embodiment, the method of performing includes providing compiled code having at least one thread, where each of the at least one thread includes a respective plurality of blocks and each respective block includes a respective pre-fetch component and a respective execute component. The method also includes performing a first pre-fetch component from a first block of a first thread of the at least one thread, performing a first additional component after the first pre-fetch component has been performed, and performing a first execute component from the first block of the first thread. The first execute component is performed after the first additional component has been performed, and the first additional component is from either a second thread or another block of the first thread that is not the first block.

Abstract: A method for handling a request of storage on a serial fabric comprising formatting an address for communication on a serial fabric into a plurality of fields including a field comprising at least one set selection bit and a field comprising at least one tag bit. The address is communicated on the serial fabric with the field comprising the at least one set selection bit communicated first.

Abstract: A method for maintaining cache coherence comprises coordinating operations among a plurality of processors distributed among a plurality of nodes coupled by an interconnect fabric and managing cache coherence in a plurality of memory directories respectively associated with the processor plurality in combination with a node controller directory cache associated with a node controller coupled between the processor plurality and the interconnect fabric. The method further comprises maintaining memory coherence directory information comprising identifying processors within a node in a first portion of bits of a memory directory entry coupled to an associated processor in the node and identifying subsets of processors external to the node in the system in a second portion of bits.

Abstract: A video sequence is enhanced by selecting a reference video frame and at least one auxiliary video frame from the video sequence. The information from the reference frame and the auxiliary frame are combined based on measurements of the displacement of objects between the reference frame and each of the auxiliary video frames. Video and multimedia presentations are then generated using the enhanced video frame combining information from the reference video frame and the at least one auxiliary video frame.