Abstract: A set of piconets and corresponding methods and computer programs may reduce contention time between piconets. In one embodiment, a seven-length code architecture may be used with group(s) of bands so that contention time cannot exceed 1/7 of the time. Up to seven different bands can be used within each group. When less than seven bands are used (e.g., three or six), at least one of the bands may be assigned to more than one dwell time during a time span. Alternatively, each dwell time within the time span may be assigned to a different band. The state may be changed as needed or desired. Substitution of extra bands may also be used. Using either scheme (repeated bands or changing states), a prime-number architecture can be used with a non-prime number of different bands. Simultaneous communications using at least two bands within a piconet may be used.

Abstract: Apparatuses, systems and methods for transmitting and receiving modulated impulse radio signals. An impulse radio receiver includes a time base, a precision timing generator, a template generator, a delay, first and second correlators, a data detector and a time base adjustor. The time base produces a periodic timing signal that is used by the precision timing generator to produce a timing trigger signal. The template generator uses the timing trigger signal to produce a template signal. A delay receives the template signal and outputs a delayed template signal. When an impulse radio signal is received, the first correlator correlates the received impulse radio signal with the template signal to produce a first correlator output signal, and the second correlator correlates the received impulse radio signal with the delayed template signal to produce a second correlator output signal. The data detector produces a data signal based on at least the first correlator output signal.

Abstract: A graphics accelerator includes a vertex input for receiving vertex data, an output for forwarding processed data, and a processor coupled with the vertex input and output. The graphics accelerator also includes an instruction input that receives instructions for processing the vertex data received from the vertex input. The processor is responsive to wide word instructions.

Abstract: A method for generating code sequences having good correlation properties comprising steps of selecting a code length comprising a number of chips, selecting a ruler which defines the position of non-zero values within the chips, and overlaying the non-zero values with an amplitude pattern.

Abstract: An ultra wideband system employing a threshold to detect signal quality during acquisition wherein the threshold is adjusted based on signal characteristics such as packet traffic rate, packet loss rate, and packet loss fraction. In one embodiment, the threshold is adjusted by adjusting the gain of a variable gain stage ahead of the threshold. In another embodiment, gain and threshold are adjusted in a coordinated manner wherein gain is adjusted for low signal levels and threshold is adjusted for high signal levels. In one embodiment, packet traffic rate is evaluated over an interval based on maximum packet length, number of monitor packets, and inter-packet delay. In a further embodiment, multiple ramp builders are operated in parallel at multiple code offset values to generate signal statistics to compare with the threshold. Embodiments are disclosed wherein the thresholds are adaptively adjusted based on signal performance characteristics or the multipath environment.

Abstract: A graphics accelerator includes a vertex input for receiving vertex data, an output for forwarding processed data, and a processor coupled with the vertex input and output. The graphics accelerator also includes an instruction input that receives instructions for processing the vertex data received from the vertex input. The processor is responsive to wide word instructions.

Abstract: A graphics accelerator includes a vertex input for receiving vertex data, an output for forwarding processed data, and a processor coupled with the vertex input and output. The graphics accelerator also includes an instruction input that receives instructions for processing the vertex data received from the vertex input. The processor is responsive to wide word instructions.

Abstract: A graphics accelerator includes a vertex input for receiving vertex data, an output for forwarding processed data, and a processor coupled with the vertex input and output. The graphics accelerator also includes an instruction input that receives instructions for processing the vertex data received from the vertex input. The processor is responsive to wide word instructions.

Abstract: An apparatus for processing a graphics request stream begins processing subsequent vertex data while processing previous vertex data. To that end, the apparatus has a vertex assembler having an input for receiving graphics requests, and a processor (coupled to the vertex assembler) for processing received graphics requests. The processor provides a headstart signal to the vertex assembler to indicate that the processor is processing a new graphics request. Upon receipt of the headstart signal, the vertex assembler causes the processor to restart processing of the new graphics request if the new request is determined to have not been properly assembled.

Abstract: A graphics processor for processing vertices of a polygon includes an input for receiving an instruction for processing a given vertex, memory for storing a first lookup table and a second lookup table, and an interpolation engine that, responsive to receipt of the instruction from the input, selects one of the lookup tables, determines table output from the one of the lookup tables, and produces an output value based upon the table output and data relating to the given vertex. Each of the first and second lookup tables may correspond to a selected function and contains table output as a function of an input value. The input value corresponds to data relating to the given vertex.

Abstract: The present invention relates to a method and apparatus for efficiently outputting words from an N-way set-associative cache. In one embodiment, the cache tags contain information indicating which set contains a line holding data succeeding the last word in the line accessed during a cache read. For a cache which outputs M words for each access, when the addressed word is within M-1 words of the end of the line, the cache will output all the words from the accessed word to the end of the line and the remainder of the M words from a succeeding line in whatever set is indicated by the pointer.