Abstract: An apparatus identifies redundancy memory cells that are selected to replace defective memory cells of a memory matrix that communicates with a data bus. A redundancy address register is associated with one of the redundancy memory cells. The redundancy address register stores a default state until it is programmed with an address of one of the defective memory cells. A control circuit generates a test signal during an identification mode. A detect circuit is coupled to the control circuit and to the redundancy address register and generates a default-detect signal in response to the test signal when the redundancy address register contains the default state. A data-bus multiplexer that is coupled to the redundancy-cell selection circuit, the data bus, and the control circuit couples the default detect signal to the data bus in response to the test signal.

Abstract: A fuse protection circuit for an electrically programmable read only memory circuit consists of a fusing element such as an antifuse connected between a bitline and the drain of the access transistor, and which is susceptible to inadvertent activation due to programming voltages applied to the bitline when the access transistor is not being addressed. The fusing element is protected from such inadvertent activation by the addition of a capacitor between the drain of the access transistor and the bitline.

Abstract: A field effect transistor storage device for use in programmable read-only memories of the type employing a floating gate and a control gate overlying and aligned with the floating gate. An erase gate is provided adjacent at least one edge of the floating gate for removing charge stored on the floating gate. A method of electrically erasing the storage device includes holding the control gate at a fixed potential to thereby hold the floating gate at a substantially fixed potential while a relatively low voltage is applied to the erase gate to remove charge stored on the floating gate.

Abstract: A programmable read only memory (PROM) integrated circuit is constructed with two new operating modes: a bit-check mode and a deprogramming mode. In the bit-check mode, circuitry is provided to readily determine the apparent threshold voltage of each programmable transistor within the PROM. In the deprogrammable mode, circuitry is provided to simultaneously subject all programmable transistors within the PROM to a deprogramming stress. The bit-check mode provides a rapid programming method, and the bit-check mode and deprogramming mode are utilized in conjunction with each other to provide a rapid and thorough testing method.

Abstract: A MOSFET random access memory having an extremely low current load memory cell is disclosed. The memory cell comprises a cross-coupled binary stage in which one or more paths to ground can be selectively switched on or off through true and complement data nodes. Impedance means connect a power supply node to the data nodes for charging the data nodes to predetermined voltage levels. The impedance means comprise an intrinsic-extrinsic junction of a substantially pure, intrinsic semiconductor material and a diffusion of extrinsic conductivity impurities disposed within a region of the intrinsic semiconductor material. The impedance means is formed by an isoplanar silicon gate process as an integral portion of a polycrystalline silicon strip which interconnects the power supply node to a data node. A portion of the polycrystalline silicon strip is extended from the data node to form the gate of the transistor to which it is cross-coupled.

Abstract: Block redundancy is utilized to improve yield and lower die cost for an electrically programmable read only memory (EPROM). The EPROM is organized 8Kx8 with four primary memory blocks on each side of a central row decoder. Each block includes an array of memory cells, column select, column decode, sense amp, data buffer and other overhead circuitry. One block of redundant circuitry is also provided for each set of four blocks and includes a redundant memory matrix, a redundant column decoder, a redundant column select, a redundant sense amp and a redundant data buffer. Incorporated within each primary memory block is a multiplex logic circuit which is independently programmable to selectively disconnect the associated primary memory block and substitute the redundant memory block, including the redundant column decoder, column select, sense amp and data buffer.

Abstract: A MOSFET random access memory having an extremely low current load memory cell is disclosed. The memory cell comprises a cross-coupled binary stage in which one or more paths to ground can be selectively switched on or off through true and complement data nodes. Impedance means connect a power supply node to the data nodes for charging the data nodes to predetermined voltage levels. The impedance means comprise an intrinsic-extrinsic junction of a substantially pure, intrinsic semiconductor material and a diffusion of extrinsic conductivity impurities disposed within a region of the intrinsic semiconductor material. The impedance means is formed by an isoplanar silicon gate process as an integral portion of a polycrystalline silicon strip which interconnects the power supply node to a data node. A portion of the polycrystalline silicon strip is extended from the data node to form the gate of the transistor to which it is cross-coupled.

Abstract: The invention disclosed herein is a high performance inverter circuit using MOSFETs having varying threshold voltages produced by selectively varying ion implantation doses in the channels of the MOSFETs and using a slightly depletion type MOSFET, rather than a conventional depletion type, in the output stage.

Abstract: A symmetrical structural layout for the principal components of each cell in a group of four mutually contiguous cells of an array of memory cells is disclosed. A common drain supply node is centrally disposed within the group and is coincident with the intersection of first and second mutually perpendicular axes of symmetry. Corresponding components of contiguous cells in each row and column are symmetrically disposed with respect to each of the first and second axes of symmetry. In a preferred embodiment, the principal components of each cell include a plurality of insulated gate field-effect transistors each having a source diffusion region and a drain diffusion region formed within the substrate and a plurality of impedance devices electrically connecting the common drain supply node to the drain diffusions of the transistors in each cell.